IA186EB/IA188EB
Data Sheet
8-Bit/16-Bit Microcontrollers
July 10, 2011
Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
ale
Description
Name
ale
PLCC
6
LQFP
75
PQFP
38
address latch enable. Output. Active High.
This signal is used to latch the address
information during the address portion of a bus
cycle.
bclk0
bclk1
bhe_n
p2.5/bclk0
p2.2/bclk1
bhe_n
54
59
7
41
46
76
4
9
baud clock, Serial Port 0. Input. The bclk0 pin
can be used to provide an alternate clock
source for Serial Port 0. The input clock rate
cannot be greater than one-half the operating
frequency of the IA186EB.
baud clock, Serial Port 1. Input. The bclk1 pin
can be used to provide an alternate clock
source for Serial Port 1. The input clock rate
cannot be greater than one-half the operating
frequency of the IA186EB.
39
byte high enable. Output. Active Low. When
bhe_n is asserted (low), it indicates that the
bus cycle in progress is transferring data over
the upper half of the data bus.
bhe_n is
multi-
bhe_n is
multi-
Additionally, bhe_n and ad0 encode the
following bus information:
plexed
with
plexed with
refresh_n
ad0
bhe_n
Bus Status
refresh_n
0
0
1
1
0
1
0
1
Word Transfer
Even Byte Transfer
Odd Byte Transfer
Refresh Operation
Note: bhe_n is multiplexed with refresh_n.
busy
test_n/busy
14
NA
NA
busy. Input. Active High. When the busy
input is asserted, it causes the IA186EB to
suspend operation during the execution of the
Intel 80C187 Numerics Coprocessor
instructions. Operation resumes when the pin
is sampled low. This applies to the PLCC
package only.
IA211080314-13
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