IA186EB/IA188EB
8-Bit/16-Bit Microcontrollers
Data Sheet
July 10, 2011
4.1.3
Interrupt Control Unit
The IA186EB/IA188EB can receive interrupts from a number of sources, both internal and
external. The interrupt control unit serves to merge these requests on a priority basis, for
individual service by the CPU. Each interrupt source can be independently masked by the
Interrupt Control Unit (ICU) or all interrupts can be globally masked by the CPU.
Internal interrupt sources include the Timers and Serial Channel 0. External interrupt sources
come from the five input pins int0–int4. The NMI interrupt pin is not controlled by the ICU and
is passed directly to the CPU. Although the Timer and Serial channel each have only one request
input to the ICU, separate vector types are generated to service individual interrupts within the
Timer and Serial channel units.
4.1.4
Timer/Counter Unit
The IA186EB/IA188EB Timer/Counter Unit (TCU) provides three 16-bit programmable timers.
Two of these are highly flexible and are connected to external pins for control or clocking. A
third timer is not connected to any external pins and can only be clocked internally. However, it
can be used to clock the other two timer channels. The TCU can be used to count external
events, time external events, generate non-repetitive waveforms, and generate timed interrupts,
etc.
4.1.5
Serial Communications Unit
The Serial Control Unit (SCU) of the IA186EB/IA188EB contains two independent channels.
Each channel is identical in operation except that only Channel 0 is supported by the integrated
interrupt controller (Channel 1 has an external interrupt pin). Each channel has its own baud rate
generator that is independent of the Timer/Counter Unit, and can be internally or externally
clocked at up to one half the IA186EB/IA188EB operating frequency.
Independent baud rate generators are provided for each of the serial channels. For the
asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit
register logic. A 1x baud clock is provided in the synchronous mode.
4.1.6
Chip-Select Unit
The IA186EB/IA188EB Chip-Select Unit (CSU) integrates logic that provides up to ten
programmable chip-selects to access both memories and peripherals. In addition, each chip
select can be programmed to automatically insert additional clocks (wait-states) into the current
bus cycle and automatically terminate a bus cycle independent of the condition of the ready input
pin.
IA211080314-13
UNCONTROLLED WHEN PRINTED OR COPIED
Page 47 of 85
Customer Support:
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
