IA186EB/IA188EB
Data Sheet
8-Bit/16-Bit Microcontrollers
July 10, 2011
Table 21. Instruction Set Timing (Continued)
Clock Cycles
Instruction
SHL Register/Memory by CL
IA186EB
1/20
IA188EB
1/24
Comments
register/memory
SHL Register/Memory by
Count
1/11
1/24
SHR Register/Memory by 1
1/5
1/24
1/28
1/24
SHR Register/Memory by CL
1/20
1/11
SHR Register/Memory by
Count
SS
STC
1
1
1
–
–
-
1
1
1
SUB Immediate from
accumulator
SUB Immediate from
register/memory
SUB Register/memory and
register to either
STD
STI
STOS
STOS (repeated n times)
TEST Immediate data and
accumulator
1/11
1/15
register/memory
1/28
1/40
1
1
6
–
–
–
–
–
1
1
8
6+4n
1
8+8n
1
TEST Immediate data and
register/memory
TEST Register/memory and
register
1/16
1/12
register/memory
register/memory
1/16
1/20
WAIT
XCHG Register with
accumulator
1
2
test_n = 0
1
2
–
XCHG Register/memory with
register
3/16
register/memory
3/20
XLAT
16
1
–
8
1
XOR Immediate to accumulator
–
XOR Immediate to
register/memory
1/11
1/32
register/memory
XOR Register/memory and
register to either
1/16
1/32
register/memory
IA211080314-13
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