IN24LC04B/08B
Figure 2. Bus timing Start/Stop
AC CHARACTERISTICS
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
T
SU:STA
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
Output fall time from V
IH
min
to V
IL
max
Input filter spike suppres-sion
(SDA & SCL pins)
Write cycle time
T
HD:DAT
T
SU:DAT
T
SU:STO
T
AA
T
BUF
T
OF
T
SP
T
WR
4700
0
250
4000
-
4700
-
-
-
-
-
-
-
3500
-
250
50
10
600
0
100
600
-
1300
20+0.1C
B
-
-
-
-
-
-
900
-
250
50
10
ns
ns
ns
ns
ns
ns
ns
ns
ms
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD:STA
STANDARD
MODE
Vcc = 4.5 - 5.5V
FAST MODE
Min
-
4000
4700
-
-
4000
Max
100
-
-
1000
300
-
Min
-
600
1300
-
-
600
Max
400
-
-
300
300
-
Units Remarks
kHz
ns
ns
ns Note 2
ns Note 2
ns
After this period the
first clock pulse is
generated
Only relevant for
repeated START
condition
Note 1
Time the bus must be
free before a new
transmission can start
Note2,
C
B
≤100pF
Note 3
Byte or Page
mode
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined
region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or
STOP conditions.
Note 2: Not 100% tested. C
B
=
total capacitance of one bus line in pF.
Note 3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide
improved noise and spike suppression. This eliminates the need for a Ti specification for standard
operation.
3
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