IN24LC16
PAGE WRITE
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle
is complete (this feature can be used to maximize
bus throughput). Once the stop condition for a write
command has been issued from the master, the
device initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves
the master sending a start condition followed by the
control byte for a write command (R/W = 0). If the
device is still busy with the write cycle, then no ACK
will be returned. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next read or write command.
WRITE PROTECTION
The 24LC16B can be used as a serial ROM when
the WP pin is connected to VCC. Programming will
be inhibited and the entire memory will be write-
protected.
READ OPERATION
Read operations are initiated in the same way as
write operations with the exception that the R/W bit
of the slave address is set to one. There are three
basic types of read operations: current address
read, random read, and sequential read.
ACKNOWLEDGE POLLING FLOW
Current Address Read
The 24LC16B contains an address counter that maintains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access (either a read or write operation) was to address n,
the next current address read operation would access data from address n + 1. Upon receipt of the slave
address with R/W bit set to one, the 24LC16B issues an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does generate a stop condition and the 24LC16B
discontinues transmission
Random Read
Random read operations allow the master to access any memory location in a random manner. To perform
this type of read operation, first the word address must be set. This is done by sending the word address to
the 24LC16B as part of a write operation. After the word address is sent, the master generates a start
condition following the acknowledge. This terminates the write operation, but not before the internal address
pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LC16B
will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the 24LC16B discontinues transmission (Figure 7-2).
Sequential Read
Sequential reads are initiated in the same way as a random read except that after the 24LC16B transmits
the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This
directs the 24LC16B to transmit the next sequentially addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC16B contains an internal address pointer which is incremented by one
at the completion of each operation. This address pointer allows the entire memory contents to be serially
read during one operation.
Noise Protection
7
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