IZ44780
TERMINAL DESCRIPTION
Pin
V
DD
V
SS
V
1
– V
5
SEG1–
SEG40
COM1–
COM16
OSC1
OSC2
INPUT/OUTPU
T
Power
Negative Supply
Voltage
Segment output
Common output
Oscillator
Name
Operating Voltage
DESCRIPTION
For logical circuit (+5V
±
10%)
0V(GND)
Bias voltage level for LCD driving
Segment signal output for LCD driving
Common signal output for LCD driving
Both pin connected to Rf resistor or
ceramic resonator for internal oscillator
circuit. In case of external frequency use
only, the frequency is input to OSC1
terminal.
Clock output terminal for the serially
transferred data to be latched to the driver.
Clock output terminal used when D
terminal data output shifts the inside of the
driver.
The alternating signal to convert LCD
drive waveform to AC.
Character pattern data, which is
corresponding to each common signal, is
supplied to driver serially.
High
Selection
Low
Non selection
Start anable signal to read or write the data
R/W signal input is used to select the
read/write mode
High
Read mode
Low
Write mode
Register selection input
High
Data register (for read
and write)
Low
Instruction register (for
write), Busy flag,
address counter (for
read)
Used for data transfer between the MPU
and IZ44780. These terminals are for data
bus with bidirectional three-state.
Initial 4 bit (DB
0
-DB
3
) are not used during
4 bit operation (DB
7
can be used as a busy
flag)
MPU
INTERFACE
Power
Supply
Output
Output
Input
Output
LCD
LCD
Resistor or
Ceramic
Resonator
CLK1
CLK2
Output
Data latch clock
Data shift clock
HD44100,
KS0065,
IZ0065
M
D
Alternated signal
for LCD driver
output
Display data
interface
E
R/W
Input
Enable
Read/Write
RS
Register select
DB
0
–
DB
7
Input/Output
Data interface
7
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