IN74AC299
FUNCTION TABLE
Inputs
Mode
Reset
Mode
Select
S
2
Reset
L
L
L
Shift
Right
H
H
H
Shift
Left
H
H
H
Parallel
Load
Hold
H
H
H
H
X
L
H
L
L
L
H
H
H
H
L
L
L
S
1
L
X
H
H
H
H
L
L
L
H
L
L
L
Output
Enables
OE1
L
L
X
H
X
L
H
X
L
X
H
X
L
OE2
L
L
X
X
H
L
X
H
L
X
X
H
L
X
X
X
X
X
X
Clock
Serial
Inputs
D
A
D
H
X
X
X
D
D
D
X
X
X
X
X
X
X
X
X
X
X
X
X
D
D
D
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D
D
D
Q
B
Q
B
Q
B
P
A
P
A
P
A
P
A
L
L
L
Q
G
Q
G
Q
G
D
D
D
P
H
P
H
P
H
P
H
Response
P
A
/ P
B
/ P
C
/ P
D
/ P
E
/ P
F
/ P
G
/ P
H
/ Q
A
’ Q
H
’
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
A
through Q
H
=Z
Shift Right: Q
A
through Q
H
=Z;
D
A
F
A
; F
A
F
B
; etc
Shift Right: Q
A
through Q
H
=Z;
D
A
F
A
; F
A
F
B
; etc
Shift Right: D
A
F
A
=Q
A
;
F
A
F
B
=Q
B
; etc
Shift Left: Q
A
through Q
H
=Z;
D
H
F
H
; F
H
F
G
; etc
Shift Left: Q
A
through Q
H
=Z;
D
H
F
H
; F
H
F
G
; etc
Shift Left: D
H
F
H
=Q
H
;
F
H
F
G
=Q
G
; etc
Parallel Load:P
N
F
N
Hold: Q
A
through Q
H
=Z; F
N
=F
N
Hold: Q
A
through Q
H
=Z; F
N
=F
N
Hold: Q
N
=Q
H
Z = high impedance
D = data on serial input
F = flip-flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the high-
impedance state; however, sequential operation or clearing of the register is not affected.
391
INTEGRAL [ INTEGRAL CORP. ]
