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IN74ACT373DW 参数 Datasheet PDF下载

IN74ACT373DW图片预览
型号: IN74ACT373DW
PDF下载: 下载PDF文件 查看货源
内容描述: 八路三态同相透明锁存器 [OCTAL 3-STATE NONINVERTING TRANSPARENT LATCH]
分类和应用: 锁存器
文件页数/大小: 5 页 / 232 K
品牌: INTEGRAL [ INTEGRAL CORP. ]
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IN74ACT373
AC ELECTRICAL CHARACTERISTICS(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25
°C
-40°C to
85°C
Min Max Min Max
t
PLH
Propagation Delay, Input D to Q (Figure 1)
2.5
10
1.5
11.5
t
PHL
Propagation Delay, Input D to Q (Figure 1)
2.0
10
1.5
11.5
t
PLH
Propagation Delay, Latch Enable to Q 2.5
11
2.0
11.5
(Figure 2)
t
PHL
Propagation Delay, Latch Enable to Q 2.0
10
1.5
11.5
(Figure 2)
t
PZH
Propagation Delay, Output Enable to Q 2.0
9.5
1.5
10.5
(Figure 3)
t
PZL
Propagation Delay, Output Enable to Q 2.0
9.0
1.5
10.5
(Figure 3)
t
PHZ
Propagation Delay, Output Enable to Q 2.5
11
2.5
12.5
(Figure 3)
t
PLZ
Propagation Delay, Output Enable to Q 1.5
8.5
1.0
10
(Figure 3)
C
IN
Maximum Input Capacitance
4.5
4.5
Typical @25°C,V
CC
=5.0 V
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
pF
C
PD
Power Dissipation Capacitance
pF
TIMING REQUIREMENTS(V
CC
=5.0 V
±
10%, C
L
=50pF, Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25
°C
-40°C to
85°C
t
su
Minimum Setup Time, Input D to Latch
7.0
8.0
Enable (Figure 4)
t
h
Minimum Hold Time, Latch Enable to
0
1.0
Input D (Figure 4)
t
w
Minimum Pulse Width, Latch Enable
2.0
8.0
(Figure 2)
Unit
ns
ns
ns
4