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IN74HC4094D 参数 Datasheet PDF下载

IN74HC4094D图片预览
型号: IN74HC4094D
PDF下载: 下载PDF文件 查看货源
内容描述: 8位串行输入移位寄存器锁存三态输出的高性能硅栅CMOS [8-Bit Serial-Input Shift Register With Latched 3-State Outputs High-Performance Silicon-Gate CMOS]
分类和应用: 移位寄存器
文件页数/大小: 7 页 / 181 K
品牌: INTEGRAL [ INTEGRAL CORP. ]
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IN74HC4094
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
Parameter
V
Guaranteed Limit
25
°C
to
-55°C
6
30
35
150
30
26
195
40
33
125
25
21
175
35
30
10
15
≤85°C
≤125°C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
Maximum Propagation Delay, Clock to SQ
H
(Figures 1 and 5)
Maximum Propagation Delay, Clock to Q
A
-Q
H
(Figures 2 and 5)
Maximum Propagation Delay ,Output Enable to
Q
A
-Q
H
(Figures 3 and 6)
Maximum Propagation Delay ,Output Enable to
Q
A
-Q
H
(Figures 3 and 6)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State), Q
A
-Q
H
Power Dissipation Capacitance (Per Package)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
5
25
28
190
38
33
245
50
42
155
31
26
220
44
37
10
15
4
20
23
225
45
38
295
60
50
190
38
32
265
53
45
10
15
MHz
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZL
, t
PZH
ns
C
IN
C
OUT
pF
pF
Typical @25°C,V
CC
=5.0 V
300
pF
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
su
Parameter
Minimum Setup Time, Serial Data
Input A to Clock (Figure 4)
Minimum Hold Time, Clock to Data
Input A (Figure 4)
Minimum Pulse Width, Strobe
(Figure 1)
Maximum Input Rise and Fall Times
(Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
25
°C
to
-55°C
50
10
9.0
3
3
3
80
16
14
1000
500
400
≤85°C
65
13
11
3
3
3
100
20
17
1000
500
400
≤125°C
75
15
13
3
3
3
120
24
20
1000
500
400
Unit
ns
t
h
ns
t
w
ns
t
r
, t
f
ns
518