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IN74HC573AN 参数 Datasheet PDF下载

IN74HC573AN图片预览
型号: IN74HC573AN
PDF下载: 下载PDF文件 查看货源
内容描述: 八路三态同相透明锁存器 [Octal 3-State Noninverting Transparent Latch]
分类和应用: 触发器锁存器
文件页数/大小: 5 页 / 120 K
品牌: INTEGRAL [ INTEGRAL CORP. ]
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IN74HC573A
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
Parameter
V
Guaranteed Limit
25
°C
to
-55°C
150
30
26
160
32
27
150
30
26
150
30
26
60
12
10
10
15
≤85°C
≤125°C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
Maximum Propagation Delay,Latch Enable
to Q (Figures 2 and 5)
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Enabled
Output)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
190
38
33
200
40
34
190
38
33
190
38
33
75
15
13
10
15
225
45
38
240
48
41
225
45
38
225
45
38
90
18
15
10
15
ns
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZH
, t
PZL
ns
t
TLH
, t
THL
ns
C
IN
C
OUT
pF
pF
Typical @25°C,V
CC
=5.0 V
23
pF
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
SU
Parameter
Minimum Setup Time, Input D
to Latch Enable
(Figure 4)
Minimum Hold Time, Latch
Enable to Input D
(Figure 4)
Minimum Pulse Width, Latch
Enable (Figure 2)
Maximum Input Rise and Fall
Times (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
25
°C
to
-55°C
50
10
9
5
5
5
75
15
13
1000
500
400
Guaranteed Limit
≤85°C
65
13
11
5
5
5
95
19
16
1000
500
400
≤125°C
75
15
13
5
5
5
110
22
19
1000
500
400
Unit
ns
t
h
ns
t
w
ns
t
r,
t
f
ns
406