82551IT — Networking Silicon
5.7
Media Independent Interface (MII) Management Interface.................................34
6.0
Physical Layer Functional Description .............................................................................35
6.1
100BASE-TX PHY Unit.......................................................................................35
6.1.1 100BASE-TX Transmit Clock Generation..............................................35
6.1.2 100BASE-TX Transmit Blocks ...............................................................35
6.1.3 100BASE-TX Receive Blocks ................................................................35
6.1.4 100BASE-TX Link Integrity Auto-Negotiation.........................................36
10BASE-T PHY Functions ..................................................................................36
6.2.1 10BASE-T Transmit Clock Generation...................................................36
6.2.2 10BASE-T Transmit Blocks....................................................................36
6.2.3 10BASE-T Receive Blocks.....................................................................36
6.2.4 10BASE-T Link Integrity and Full Duplex...............................................37
Auto-Negotiation .................................................................................................37
6.3.1 Description .............................................................................................37
6.3.2 Parallel Detect and Auto-Negotiation.....................................................37
LED Description ..................................................................................................38
6.2
6.3
6.4
7.0
Configuration Registers....................................................................................................41
7.1
Function 0: LAN (Ethernet) PCI Configuration Space.........................................41
7.1.1 PCI Vendor ID and Device ID Registers ................................................41
7.1.2 PCI Command Register .........................................................................42
7.1.3 PCI Status Register................................................................................43
7.1.4 PCI Revision ID Register........................................................................45
7.1.5 PCI Class Code Register .......................................................................45
7.1.6 PCI Cache Line Size Register................................................................45
7.1.7 PCI Latency Timer .................................................................................45
7.1.8 PCI Header Type ...................................................................................45
7.1.9 PCI Base Address Registers..................................................................46
7.1.10 Base Address Registry Summary ..........................................................47
7.1.11 PCI Subsystem Vendor ID and Subsystem ID Registers.......................47
7.1.12 Capability Pointer ...................................................................................48
7.1.13 Interrupt Line Register............................................................................48
7.1.14 Interrupt Pin Register .............................................................................48
7.1.15 Minimum Grant Register ........................................................................49
7.1.16 Maximum Latency Register....................................................................49
7.1.17 Capability ID Register ............................................................................49
7.1.18 Next Item Pointer ...................................................................................49
7.1.19 Power Management Capabilities Register .............................................49
7.1.20 Power Management Control/Status Register (PMCSR).........................50
7.1.21 Data Register .........................................................................................51
8.0
Control/Status Registers ..................................................................................................53
8.1
LAN (Ethernet) Control/Status Registers ............................................................53
8.1.1 System Control Block Status Word........................................................54
8.1.2 System Control Block Command Word..................................................55
8.1.3 System Control Block General Pointer...................................................55
8.1.4 PORT .....................................................................................................55
8.1.5 Flash Control Register ...........................................................................55
8.1.6 EEPROM Control Register.....................................................................56
8.1.7 Management Data Interface Control Register........................................56
iv
Datasheet
INTEL [ INTEL ]
