1-Gbit P30 Family
1.0
Introduction
This document provides information about the Intel StrataFlash® Embedded Memory (P30) device
and describes its features, operation, and specifications.
1.1
Nomenclature
1.8 V :
3.0 V :
9.0 V :
V
CC
(core) voltage range of 1.7 V – 2.0 V
V
CCQ
(I/O) voltage range of 1.7 V – 3.6 V
V
PP
voltage range of 8.5 V – 9.5 V
A group of bits, bytes,1-Gbit P30 Family or words within the
flash memory array that erase simultaneously when the Erase
command is issued to the device. The 1-Gbit P30 Family has
two block sizes: 32-KByte and 128-KByte.
An array block that is usually used to store code and/or data.
Main blocks are larger than parameter blocks.
An array block that is usually used to store frequently changing
data or small system parameters that traditionally would be
stored in EEPROM.
A device with its parameter blocks located at the highest
physical address of its memory map.
A device with its parameter blocks located at the lowest
physical address of its memory map.
Block :
Main block :
Parameter block :
Top parameter device :
Bottom parameter device :
1.2
Acronyms
BEFP :
CUI :
MLC :
OTP :
PLR :
PR :
RCR :
Buffer Enhanced Factory Programming
Command User Interface
Multi-Level Cell
One-Time Programmable
Protection Lock Register
Protection Register
Read Configuration Register
Datasheet
Intel StrataFlash
®
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
7
INTEL [ INTEL CORPORATION ]
