28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.6.1
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RP# to the
system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when VCC voltages are above VLKO. Since
both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs.
By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
3.6.2
V
, V and RP# Transitions
CC PP
The CUI latches commands as issued by system software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
V
CC transitions above VLKO (Lockout voltage), is read array mode.
After any program or block erase operation is complete (even after VPP transitions down to
V
PPLK), the CUI must be reset to read array mode via the Read Array command if access to the
flash memory array is desired.
3.7
Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling. System
designers should consider three supply current issues:
1. Standby current levels (ICCS
2. Read current levels (ICCR
)
)
3. Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor selection will suppress these transient voltage
peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and
GND, and between its VPP and GND. These high-frequency, inherently low-inductance capacitors
should be placed as close as possible to the package leads.
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17
INTEL [ INTEL ]
