ISL75051SEH
Pin Configuration
ISL75051SEH
(18 LD CDFP)
TOP VIEW
GND
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VADJ
BYP
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PG
VIN
VIN
VIN
VIN
VIN
VIN
OCP
EN
GND
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
12, 13, 14
15, 16, 17
V
Input supply pins
IN
18
1
PG
V
in regulation signal. Logic low defines when V
OUT
is not in regulation. Must be grounded if not used.
OUT
GND
GND pin
2, 3, 4
5, 6, 7
V
Output voltage pins
OUT
8
9
VADJ
BYP
EN
VADJ pin allows V to be programmed with an external resistor divider.
OUT
To filter the internal reference, connect a 0.1µF capacitor from BYP pin to GND.
V independent chip enable. TTL and CMOS compatible.
IN
10
11
OCP
GND
Allows current limit to be programmed with an external resistor.
The top lid is connected to GND pin of the package.
Top Lid
Ordering Information
ORDERING
NUMBER
PART NUMBER
(NOTES 1, 2)
TEMP
RANGE (°C)
PACKAGE
18 Ld CDFP
PKG DWG. #
K18.D
5962R1121202VXC
5962R1121202V9A
ISL75051SRHF/PROTO
ISL75051SRHEVAL1Z
NOTES:
ISL75051SEHVF
ISL75051SEHVX
-55 to +125
-55 to +125
-55 to +125
ISL75051SRHF/PROTO
Evaluation Board
18 Ld CDFP
K18.D
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL75051SEH. For more information on MSL please see Tech Brief TB363.
FN8294.0
August 28, 2012
3
INTERSIL [ Intersil ]
