®
EL4585
Data Sheet
July 1, 2005
FN7175.3
Horizontal Genlock, 8F
SC
The EL4585 is a PLL (Phase Lock Loop) sub-system,
designed for video applications and also suitable for general
purpose use up to 36MHz. In video applications, this device
generates a TTL/CMOS-compatible pixel clock (CLK OUT)
which is a multiple of the TV horizontal scan rate and phase
locked to it.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog
composite video signal with the EL4583 sync separator. An
input signal to “coast” is provided for applications where
periodic disturbances are present in the reference video
timing such as VTR head switching. The lock detector output
indicates correct lock.
The divider ratio is four ratios for NTSC and four similar
ratios for the PAL video timing standards by external
selection of three control pins. These four ratios have been
selected for common video applications including 8F
SC
,
6F
SC
, 27MHz (CCIR 601 format) and square picture
elements used in some workstation graphics. To generate
4F
SC
, 3F
SC
, 13.5MHz (CCIR 601 format) etc., use the
EL4584, which does not have the additional divide-by-two
stage of the EL4585.
For applications where these frequencies are inappropriate
or for general purpose PLL applications the internal divider
can be bypassed and an external divider chain used.
FREQUENCIES AND DIVISORS
FUNCTION
Divisor (Note 4)
PAL F
OSC
(MHz)
Divisor (Note 4)
NTSC F
OSC
(MHz)
NOTES:
1. 6F
SC
frequencies do not yield integer divisors.
2. CCIR 601 divisors yield 1440 pixels in the active portion of each
line for NTSC and PAL.
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
for PAL.
4. Divisor does not include ÷ 2 block.
6F
SC
CCIR 601 SQUARE
(NOTE 1) (NOTE 2) (NOTE 3)
1702
26.602
1364
21.476
1728
27.0
1716
27.0
1888
29.5
1560
24.546
8F
SC
2270
35.468
1820
28.636
Features
• 36MHz, general purpose PLL
• 8F
SC
timing (use the EL4584 for 4F
SC
)
• Compatible with EL4583 sync separator
• VCXO, Xtal, or LC tank oscillator
• < 2ns jitter (VCXO)
• User-controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed popular TV scan rate clock divisors
• Single 5V, low current operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Pixel clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture in Picture) timing generator
• Text or graphics overlay timing
Ordering Information
PART
NUMBER
EL4585CN
EL4585CS
EL4585CS-T7
EL4585CS-T13
EL4585CSZ
(See Note)
EL4585CSZ-T7
(See Note)
PACKAGE
16-Pin PDIP
16-Pin SO (0.150”)
16-Pin SO (0.150”)
16-Pin SO (0.150”)
16-Pin SO (0.150”)
(Pb-free)
16-Pin SO (0.150”)
(Pb-free)
TAPE &
REEL
-
-
7”
13”
-
7”
13”
PKG. DWG.
#
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
EL4585CSZ-T13 16-Pin SO (0.150”)
(See Note)
(Pb-free)
*For 3F
SC
and 4F
SC
clock frequency operation, see EL4584
datasheet.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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