The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
P
DMAX
=
Σi [
V
S
×
I
SMAX
+
(
V
S
+
–
V
OUT
i
) ×
I
LOAD
i
]
POWER DISSIPATION (W)
3.5
3
2.5
2
1.5
1
0.5
0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD -
HTSSOP EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
2.632W
HTSSOP14
θ
JA
=38°C/W
when sourcing, and:
P
DMAX
=
Σi [
V
S
×
I
SMAX
+
(
V
OUT
i
–
V
S
-
) ×
I
LOAD
i
]
when sinking,
where:
• i = 1 to 2 for dual and 1 to 4 for quad
• V
S
= Total supply voltage
• I
SMAX
= Maximum supply current per amplifier
• V
OUT
i = Maximum output voltage of the application
• I
LOAD
i = Load current
If we set the two P
DMAX
equations equal to each other, we
can solve for R
LOAD
i to avoid device overheat. Figures 29,
30, and 31 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if P
DMAX
exceeds the device's power
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figures 29, 30 & 31.
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5111, EL5211, and EL5411 can provide gain at high
frequency. As with any high-frequency device, good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the V
S
- pin is
connected to ground, a 0.1µF ceramic capacitor should be
placed from V
S
+ to pin to V
S
- pin. A 4.7µF tantalum
capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7µF capacitor may be used for
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used.
0.9
0.8
POWER DISSIPATION (W)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
694mW
HTSSOP14
θ
JA
=144°C/W
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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12
FN7119.4
INTERSIL [ INTERSIL CORPORATION ]
