EL5825
Absolute Maximum Ratings
(T
A
= 25°C)
Supply Voltage between V
S
and GND. . . . . . . . . . . . . . . . . . . .+18V
Supply Voltage between V
SD
and GND . . . . . . . V
S
and +7V (max)
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
SUPPLY
I
S
I
SD
ANALOG
V
OL
V
OH
I
SC
PSRR
t
D
V
AC
V
DROOP
R
INH
REG
BG
DIGITAL
V
IH
V
IL
F
CLK
t
S
t
H
t
LC
t
CE
t
DCO
R
SDIN
Supply Current
V
S
= 15V, V
SD
= 5V, V
REFH
= 13V, V
REFL
= 2V,
R
L
= 1.5kΩ and
C
L
= 200pF to 0V, T
A
= 25°C, unless
otherwise specified.
CONDITIONS
MIN
TYP
MAX
UNIT
DESCRIPTION
No load
7.6
0.17
9
0.35
mA
mA
Digital Supply Current
Output Swing Low
Output Swing High
Short Circuit Current
Power Supply Rejection Ratio
Program to Out Delay
Accuracy
Droop Voltage
Input Resistance @ V
REFH
, V
REFL
Load Regulation
Band Gap
Sinking 5mA (V
REFH
= 15V, V
REFL
= 0)
Sourcing 5mA (V
REFH
= 15V, V
REFL
= 0)
R
L
= 10Ω
V
S
+ is moved from 14V to 16V
14.85
100
45
50
14.95
140
60
4
20
1
34
150
mV
V
mA
dB
ms
mV
2
mV/ms
kΩ
I
OUT
= 5mA step
1.1
0.5
1.3
1.5
1.6
mV/mA
V
Logic 1 Input Voltage
Logic 0 Input Voltage
Clock Frequency
Setup Time
Hold Time
Load to Clock Time
Clock to Load Line
Clock to Out Delay Time
S
DIN
Input Resistance
Negative edge of SCLK
V
SD
-
20%
20%*
V
SD
5
20
20
20
20
10
1
V
V
MHz
ns
ns
ns
ns
ns
GΩ
2
FN7005.4
June 24, 2005
INTERSIL [ INTERSIL CORPORATION ]
