HIP6301
Simplified Power System Diagram
VSEN
PWM 1
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
PWM 2
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
MICROPROCESSOR
HIP6301
PWM 3
PWM 4
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
VID
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
Functional Pin Description
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
COMP 6
FB 7
FS/DIS 8
GND 9
VSEN 10
20 V
CC
19 PGOOD
18 PWM4
17 ISEN4
16 ISEN1
15 PWM1
14 PWM2
13 ISEN2
12 ISEN3
11 PWM3
converter. Pulling this pin to ground disables the converter
and three states the PWM outputs. See Figure 10.
GND (Pin 9)
Bias and reference ground. All signals are referenced to this
pin.
VSEN (Pin 10)
Power good monitor input. Connect to the microprocessor-
CORE voltage.
PWM1 (Pin 15), PWM2 (Pin 14), PWM3 (Pin 11) and
PWM4 (Pin 18)
PWM outputs for each driven channel in use. Connect these
pins to the PWM input of a HIP6601/2/3 driver. For systems
which use 3 channels, connect PWM4 high. Two channel
systems connect PWM3 and PWM4 high.
VID4 (Pin 1), VID3(Pin 2), VID2 (Pin 3), VID1(Pin 4)
and VID0 (Pin 5)
Voltage Identification inputs from microprocessor. These pins
respond to TTL and 3.3V logic signals. The HIP6301 decodes
VID bits to establish the output voltage. See Table 1.
ISEN1 (Pin 16), ISEN2 (Pin 13), ISEN3 (Pin 12) and
ISEN4 (Pin 17)
Current sense inputs from the individual converter channel’s
phase nodes. Unused sense lines MUST be left open.
COMP (Pin 6)
Output of the internal error amplifier. Connect this pin to the
external feedback and compensation network.
PGOOD (Pin 19)
Power good. This pin provides a logic-high signal when the
microprocessor CORE voltage (VSEN pin) is within specified
limits and Soft-Start has timed out.
FB (Pin 7)
Inverting input of the internal error amplifier.
FS/DIS (Pin 8)
Channel frequency, F
SW
, select and disable. A resistor from
this pin to ground sets the switching frequency of the
V
CC
(Pin 20)
Bias supply. Connect this pin to a 5V supply.
3
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