HIP6602A
Functional Pin Descriptions
PWM1 (Pin 1) and PWM2 (Pin 2)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFETs. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
VCC (Pin 14)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND. To prevent forward
biasing an internal diode, this pin should be more positive
then PVCC during converter start-up.
GND (Pin 3)
Bias and reference ground. All signals are referenced to this
node.
LGATE1 (Pin 4) and LGATE2 (Pin 7)
Lower gate drive outputs. Connect to gates of the low-side
power N-Channel MOSFETs.
Description
Operation
Designed for versatility and speed, the HIP6602A two channel,
dual MOSFET driver controls both high-side and low-side
N-Channel FETs from two externally provided PWM signals.
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [TPDL
LGATE
], the
lower gate begins to fall. Typical fall times [TF
LGATE
] are
provided in the Electrical Specifications section. Adaptive
shoot-through circuitry monitors the LGATE voltage and
determines the upper gate delay time [TPDH
UGATE
] based
on how quickly the LGATE voltage drops below 2.2V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
[TR
UGATE
] and the upper MOSFET turns on.
PVCC (Pin 5)
This pin supplies the upper and lower gate drivers bias.
Connect this pin from +12V down to +5V.
PGND (Pin 6)
This pin is the power ground return for the lower gate
drivers.
PHASE2 (Pin 8) and PHASE1 (Pin 13)
Connect these pins to the source of the upper MOSFETs
and the drain of the lower MOSFETs. The PHASE voltage is
monitored for adaptive shoot-through protection. These pins
also provide a return path for the upper gate drive.
UGATE2 (Pin 9) and UGATE1 (Pin 12)
Upper gate drive outputs. Connect to gate of high-side
power N-Channel MOSFETs.
BOOT 2 (Pin 10) and BOOT 1 (Pin 11)
Floating bootstrap supply pins for the upper gate drivers.
Connect the bootstrap capacitor between these pins and the
Timing Diagram
PWM
TPDH
UGATE
TPDL
UGATE
TR
UGATE
TF
UGATE
UGATE
LGATE
TF
LGATE
TPDL
LGATE
TPDH
LGATE
TR
LGATE
5
INTERSIL [ INTERSIL CORPORATION ]
