HIP6602B
ensure safe operation at the desired frequency for the
selected MOSFETs. The total chip power dissipation is
approximated as:
_
P = 1.05 x f
SW
x V
PVCC
[
3 (Q
U1
+ Q
U2
) + (Q
L1
+ Q
L2
)
]
+ I
DDQ
x VCC
2
In Figure 2, C
U
and C
L
values are the same and frequency
is varied from 10kHz to 1.5MHz. PVCC and VCC are tied
together to a +12V supply.
Figure 3 shows the dissipation in the driver with 1nF loading
on both gates and each individually. Figure 4 is the same as
Figure 3 except the capacitance is increased to 3nF.
The impact of loading on power dissipation is shown in
Figure 5. Frequency is held constant while the gate
capacitors are varied from 1nF to 5nF. VCC and PVCC are
tied together and to a +12V supply. Figures 6, 7 and 8 show
the same characterization for PVCC tied to +5V instead of
+12V. The gate supply voltage, PVCC, within the HIP6602B
sets both upper and lower gate driver supplies at the same
5V level for the last three curves.
where f
sw
is the switching frequency of the PWM signal. Q
U
and Q
L
is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The I
DDQ
VCC product is the quiescent power
of the driver and is typically 40mW.
The 1.05 term is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. C
U
and C
L
are the upper and lower gate load
capacitors. Decoupling capacitors [0.15µF] are added to the
PVCC and VCC pins. The bootstrap capacitor value in the
test circuit is 0.01µF.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the upper MOSFETs.
P
REFRESH
=
f
SW
Q
V
=
f
SW
Q V
LOSS PVCC
U PVCC
Test Circuit
+5V OR +12V
+12V
+5V OR +12V
0.01µF
PVCC
0.15µF
BOOT1
2N7002
UGATE1
PHASE1
VCC
0.15µF
PWM1
HIP6602B
LGATE1
2N7002
C
L
100kΩ
C
U
PGND
0.01µF
BOOT2
2N7002
UGATE2
C
U
GND
PWM2
PHASE2
where Q
LOSS
is the total charge removed from the bootstrap
capacitors and provided to the upper gate loads.
LGATE2
2N7002
C
L
100kΩ
FIGURE 1. HIP6602B TEST CIRCUIT
8
FN9076.5
July 22, 2005
INTERSIL [ INTERSIL CORPORATION ]
