ICL7662
Typical Performance Curves
(See Figure 14, Test Circuit)
(Continued)
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
10
100
1K
OSCILLATOR FREQUENCY (Hz)
10K
SUPPLY CURRENT I+ (µA)
FIGURE 13. SUPPLY CURRENT AS A FUNCTION OF
OSCILLATOR FREQUENCY
NOTE:
4. These curves include in the supply current that current fed directly into the load R
L
from the V+ (See Figure 14). Thus, approximately half the
supply current goes directly to the positive side of the load, and the other half, through the ICL7662, to the negative side of the load. Ideally,
V
OUT
∼
2V
IN
, I
S
∼
2I
L
, so V
IN
x I
S
∼
V
OUT
x I
L
.
Circuit Description
The ICL7662 contains all the necessary circuitry to complete
a negative voltage converter, with the exception of 2 external
capacitors which may be inexpensive 10µF polarized
electrolytic capacitors. The mode of operation of the device
may be best understood by considering Figure 15, which
shows an idealized negative voltage converter. Capacitor C
1
is charged to a voltage, V+, for the half cycle when switches
S
1
and S
3
are closed. (Note: Switches S
2
and S
4
are open
during this half cycle.) During the second half cycle of
operation, switches S
2
and S
4
are closed, with S
1
and S
3
open, thereby shifting capacitor C
1
negatively by V+ volts.
Charge is then transferred from C
1
to C
2
such that the
voltage on C
2
is exactly V+, assuming ideal switches and no
load on C
2
. The lCL7662 approaches this ideal situation
more closely than existing non-mechanical circuits.
In the lCL7662, the 4 switches of Figure 15 are MOS power
switches; S
1
is a P-Channel device and S
2
, S
3
and S
4
are
N-Channel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of S
3
and S
4
must always remain reverse biased with respect to their
sources, but not so much as to degrade their “ON”
resistances. In addition, at circuit startup, and under output
short circuit conditions (V
OUT
= V+), the output voltage must
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.
This problem is eliminated in the ICL7662 by a logic network
which senses the output voltage (V
OUT
) together with the
level translators, and switches the substrates of S
3
and S
4
to
the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7662 is an integral part
of the anti-latchup circuitry, however its inherent voltage drop
can degrade operation at low voltages. Therefore, to improve
low voltage operation the “LV” pin should be connected to
GROUND, disabling the regulator. For supply voltages
greater than 10V the LV terminal must be left open to insure
latchup proof operation, and prevent device damage.
I
S
1
2
C
1
+
-
3
4
ICL7662
8
7
6
5
C
OSC
(NOTE)
R
L
I
L
V+
(+5V)
-V
OUT
C
2
-
10µF +
NOTE: For large value of C
OSC
(> 1000pF) the values of C
1
and C
2
should be increased to 100µF.
FIGURE 14. ICL7662 TEST CIRCUIT
6
INTERSIL [ INTERSIL CORPORATION ]
