X9241A
Flow 1. ACK Polling Sequence
The four high order bits define the instruction. The next two
bits (P1 and P0) select which one of the four potentiometers
is to be affected by the instruction. The last two bits (R1 and
R0) select one of the four registers that is to be acted upon
when a register oriented instruction is issued.
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in Figure
3. These two-byte instructions exchange data between the
WCR and one of the data registers. A transfer from a Data
Register to a WCR is essentially a write to a static RAM. The
response of the wiper to this action will be delayed t
STPWV
.
A transfer from WCR current wiper position, to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
WR
to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein the
transfer occurs between all four of the potentiometers and
one of their associated registers.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9241A; either between the host and one of the Data
Registers or directly between the host and the WCR. These
instructions are: Read WCR, read the current wiper position
of the selected pot; Write WCR, change current wiper
position of the selected pot; Read Data Register, read the
contents of the selected nonvolatile register; Write Data
Register, write a new value to the selected Data Register.
The sequence of operations is shown in Figure 4.
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9241A has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t
HIGH
) while SDA is HIGH, the
selected wiper will move one resistor segment towards the
V
H
/R
H
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V
L
/R
L
terminal. A detailed illustration
of the sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
Issue STOP
ACK
Returned?
Yes
FurTher
OperaTion?
Yes
Issue
Instruction
No
No
Issue STOP
Proceed
Proceed
Instruction Structure
The next byte sent to the X9241A contains the instruction
and register pointer information. The four most significant
bits are the instruction. The next four bits point to one of four
pots and when applicable they point to one of four
associated registers. The format is shown below in Figure 2.
Potentiometer
Select
I3
I2
I1
I0
P1
P0
R1
R0
Instructions
Register
Select
FIGURE 2. INSTRUCTION BYTE FORMAT
5
FN8164.5
December 14, 2006
INTERSIL [ INTERSIL CORPORATION ]
