欢迎访问ic37.com |
会员登录 免费注册
发布采购

X9258UV24 参数 Datasheet PDF下载

X9258UV24图片预览
型号: X9258UV24
PDF下载: 下载PDF文件 查看货源
内容描述: 低噪音/低功耗/ 2 - Wire总线/ 256水龙头 [Low Noise/Low Power/2-Wire Bus/256 Taps]
分类和应用:
文件页数/大小: 20 页 / 347 K
品牌: INTERSIL [ INTERSIL CORPORATION ]
 浏览型号X9258UV24的Datasheet PDF文件第2页浏览型号X9258UV24的Datasheet PDF文件第3页浏览型号X9258UV24的Datasheet PDF文件第4页浏览型号X9258UV24的Datasheet PDF文件第5页浏览型号X9258UV24的Datasheet PDF文件第6页浏览型号X9258UV24的Datasheet PDF文件第7页浏览型号X9258UV24的Datasheet PDF文件第8页浏览型号X9258UV24的Datasheet PDF文件第9页  
®
X9258
Low Noise/Low Power/2-Wire Bus/256 Taps
Data Sheet
May 6, 2005
FN8168.1
Quad Digital Controlled Potentiometers
(XDCP™)
FEATURES
Four potentiometers in one package
256 resistor taps/pot–0.4% resolution
2-wire serial interface
Wiper resistance, 40Ω typical @ V+ = 5V, V- = -5V
Four nonvolatile data registers for each pot
Nonvolatile storage of wiper position
Standby current < 5µA max (total package)
Power supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V- = -2.7V to -5.5V
100kΩ, 50kΩ total pot resistance
High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention – 100 years
24-lead SOIC, 24-lead TSSOP
Dual supply version of X9259
DESCRIPTION
The X9258 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
V
CC
V
SS
V+
V-
WP
SCL
SDA
A0
A1
A2
A3
R
2
R
3
R
0
R
1
Wiper
Counter
Register
(WCR)
Pot 0
V
H0
/R
H0
R
0
R
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
V
H2
/R
H2
V
L0
/R
L0
V
W0
/R
W0
R
2
R
3
V
L2
/R
L2
V
W2
/R
W2
Interface
and
Control
Circuitry
8
Data
R
0
R
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
V
W1
/R
W1
V
H1
/R
H1
R
0
R
1
Wiper
Counter
Register
(WCR)
V
W3
/R
W3
Resistor
Array
Pot 3
V
H3
/R
H3
R
2
R
3
V
L1
/R
L1
R
2
R
3
V
L3
/R
L3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.