X9258
The WCR is a volatile register; that is, its contents are
lost when the X9258 is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be
different from the value present at power-down.
Data Registers
Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the WCR. It should be noted
all operations changing data in one of these registers
is a nonvolatile operation and will take a maximum of
10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Instruction Format
Notes:
(1)
(2)
(3)
(4)
(5)
“MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
“A3 ~ A0”: stands for the device addresses sent by the master.
“X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
“I”: stands for the increment operation, SDA held high during active SCL phase (high).
“D”: stands for the decrement operation, SDA held low during active SCL phase (high).
REGISTER DESCRIPTIONS
Data Registers, (8-Bit), Nonvolatile
WP7
NV
(MSB)
WP6 WP5 WP4 WP3 WP2 WP1
NV
NV
NV
NV
NV
NV
WP0
NV
(LSB)
Four 8-bit Data Registers for each DCP. (sixteen 8-bit
registers in total).
– {D7~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the wiper counter
register on power-up.
Wiper Counter Register, (8-Bit), Volatile
WP7
WP6 WP5 WP4 WP3 WP2 WP1
WP0
Read Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR
S
opcode
addresses
A
C
P P
1 0 0 1 0 0
K
1 0
wiper position
S
(sent by slave on SDA)
A
C W W W W W W W W
K P P P P P P P P
7 6 5 4 3 2 1 0
M
A
C
K
S
T
O
P
Write Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR
S
opcode
addresses
A
C
P P
K 1 0 1 0 0 0 1 0
Data Byte
S
(sent by master on SDA)
A
C W W W W W W W W
K P P P P P P P P
7 6 5 4 3 2 1 0
S
A
C
K
S
T
O
P
Read Data Register (DR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction DR and WCR
S
opcode
addresses
A
C
R R P P
K 1 0 1 1 1 0 1 0
Data Byte
S
(sent by slave on SDA)
A
C W W W W W W W W
K P P P P P P P P
7 6 5 4 3 2 1 0
M
A
C
K
S
T
O
P
8
FN8168.1
May 6, 2005
INTERSIL [ INTERSIL CORPORATION ]
