ZL2106
Pin Descriptions(Continued)
TYPE
PIN
LABEL
(Note 1)
DESCRIPTION
31
VR
PWR
Regulated bias from internal 7V low-dropout regulator (return is PGND). Decouple with a
4.7µF capacitor to PGND.
32
33
VRA
PWR
PWR
Regulated bias from internal 5V low-dropout regulator for internal analog circuitry (return
is SGND). Decouple with a 4.7µF capacitor to SGND.
V2P5
Regulated bias from internal 2.5V low-dropout regulator for internal digital circuitry (return
is DGND). Decouple with a 10µF capacitor.
34
35
DDC
MGN
EN
I/O
Digital-DC Bus (open drain). Interoperability between Zilker Labs devices.
Margin pin. Used to enable margining of the output voltage.
Enable pin. Used to enable the device (active high).
I
I
36
ePad
SGND
PWR
Exposed thermal pad. Common return for analog signals. Connect to low impedance
ground plane.
NOTES:
1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pins. Please refer to Section “Multi-mode Pins” on page 12.
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
Ordering Information
PART NUMBER
PART
TEMP RANGE
(°C)
PKG.
DWG. #
(Notes 2, 3)
MARKING
PACKAGE
36 Ld 6mmx6mm QFN
36 Ld 6mmx6mm QFN
36 Ld 6mmx6mm QFN
ZL2106ALCN
2106
-40 to +85
-40 to +85
-40 to +85
L36.6x6A
ZL2106ALCNT (Note 1)
ZL2106ALCNTK (Note 1)
ZL2106EVAL1Z
2106
L36.6x6A
L36.6x6A
2106
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ZL2106. For more information on MSL please see
techbrief TB363.
FN6852.2
February 11, 2010
4
INTERSIL [ Intersil ]
