HIN232, HIN236, HIN237, HIN238, HIN239, HIN240, HIN241
Transmitters
The transmitters are TTL/CMOS compatible inverters which
translate the inputs to RS-232 outputs. The input logic threshold
is about 26% of V
CC
, or 1.3V for V
CC
= 5V. A logic 1 at the
input results in a voltage of between -5V and V- at the output,
and a logic 0 results in a voltage between +5V and (V+ -0.6V).
Each transmitter input has an internal 400kΩ pullup resistor so
any unused input can be left unconnected and its output
remains in its low state. The output voltage swing meets the
RS-232C specifications of
±5V
minimum with the worst case
conditions of: all transmitters driving 3kΩ minimum load
impedance, V
CC
= 4.5V, and maximum allowable operating
temperature. The transmitters have an internally limited output
slew rate which is less than 30V/µs. The outputs are short
circuit protected and can be shorted to ground indefinitely. The
powered down output impedance is a minimum of 300Ω with
±2V
applied to the outputs and V
CC
= 0V.
V+
GND
V
CC
400kΩ
T
XIN
GND < T
XIN
< V
CC
V-
300Ω
T
OUT
V- < V
TOUT
< V+
Receivers
The receiver inputs accept up to
±30V
while presenting the
required 3kΩ to 7kΩ input impedance even if the power is off
(V
CC
= 0V). The receivers have a typical input threshold of
1.3V which is within the
±3V
limits, known as the transition
region, of the RS-232 specifications. The receiver output is
0V to V
CC
. The output will be low whenever the input is
greater than 2.4V and high whenever the input is floating or
driven between +0.8V and -30V. The receivers feature 0.5V
hysteresis to improve noise rejection. The receiver Enable
line EN, when set to logic “1”, (HIN236, 239, 240, and 241)
disables the receiver outputs, placing them in the high
impedance mode. The receiver outputs are also placed in
the high impedance state when in shutdown mode.
V
CC
R
XIN
-30V < R
XIN
< +30V
5kΩ
R
OUT
GND < V
ROUT
< V
CC
FIGURE 3. RECEIVER
FIGURE 2. TRANSMITTER
T
IN
OR
R
IN
T
OUT
OR
R
OUT
V
OL
V
OL
t
PHL
t
PLH
Average Propagation Delay =
t
PHL +
t
PLH
2
FIGURE 4. PROPAGATION DELAY DEFINITION
10
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
