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LTC2263IUJ-12PBF 参数 Datasheet PDF下载

LTC2263IUJ-12PBF图片预览
型号: LTC2263IUJ-12PBF
PDF下载: 下载PDF文件 查看货源
内容描述: 12位,支持65Msps / 40Msps的/ 25Msps时的低功耗双通道ADC [12-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs]
分类和应用:
文件页数/大小: 32 页 / 1417 K
品牌: LINER [ LINEAR TECHNOLOGY ]
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LTC2265-12/
LTC2264-12/LTC2263-12
12-Bit, 65Msps/40Msps/
25Msps Low Power Dual ADCs
FEATURES
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DESCRIPTION
The LTC
®
2265-12/LTC2264-12/LTC2263-12 are 2-channel,
simultaneous sampling 12-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 71dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.3LSB
RMS
.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode) or one bit at a time (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer
allows high performance at full speed for a wide range of
clock duty cycles.
2-Channel Simultaneous Sampling ADC
71dB SNR
90dB SFDR
Low Power: 167mW/112mW/94mW Total
83mW/56mW/47mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Selectable Input Ranges: 1V
P-P
to 2V
P-P
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm
×
6mm) QFN Package
APPLICATIONS
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Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
V
DD
CH.1
ANALOG
INPUT
CH.2
ANALOG
INPUT
ENCODE
INPUT
1.8V
OV
DD
OUT1A
OUT1B
DATA
SERIALIZER
OUT2A
OUT2B
DATA
CLOCK
OUT
FRAME
GND
OGND
226512 TA01
LTC2265-12, 65Msps,
2-Tone FFT, f
IN
= 70MHz and 75MHz
0
–10
–20
AMPLITUDE (dBFS)
–30
–40
–50
–60
–70
–80
+
S/H
+
S/H
12-BIT
ADC CORE
12-BIT
ADC CORE
SERIALIZED
LVDS
OUTPUTS
PLL
–90
–100
–110
–120
0
20
10
FREQUENCY (MHz)
30
226512 TA02
22654312f
1