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L2340QC20 参数 Datasheet PDF下载

L2340QC20图片预览
型号: L2340QC20
PDF下载: 下载PDF文件 查看货源
内容描述: 数字频率合成器 [Digital Synthesizer]
分类和应用:
文件页数/大小: 11 页 / 270 K
品牌: LOGIC [ LOGIC DEVICES INCORPORATED ]
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L2340
DEVICES INCORPORATED
Digital Synthesizer
Outputs
I
15-0
— x-coordinate Data Output
ENP
1-0
32
M
AM
C
2
FM
PM
L2340 F
UNCTIONAL
B
LOCK
D
IAGRAM
AM
14-0
15
ENA
32
PH
31-0
I
15-0
is the 16-bit Cartesian x-coordi-
nate Data output port. When OEI is
HIGH, I
15-0
is forced into the high-
impedance state. I
15
is forced HIGH if
OBIQ is LOW.
Q
15-0
— y-coordinate Data Output
32
PM
32
Q
15-0
is the 16-bit Cartesian y-coordi-
nate Data output port. When OEQ is
HIGH, Q
15-0
is forced into the high-
impedance state. Q
15
is forced HIGH
if OBIQ is LOW.
Controls
ENA — Amplitude Modulation Data
Input Enable
FM
24
15
32
15
OBIQ
16
* TRANSFORM
PROCESSOR
24
16
When ENA is HIGH, AM is latched
into the input register on the rising
edge of clock. When ENA is LOW, the
value stored in the register is un-
changed.
OEQ
16
OEI
16
ENP
1-0
— Phase Modulation Data Input
Control
ENP
1-0
is the 2-bit Phase Modulation
Data Input Control that determines
one of the four modes shown in Table
1. ‘M’ is the Modulation Register and
‘C’ is the Carrier Register as shown in
the Functional Block Diagram.
I
15-0
Q
15-0
* REQUIRES 18 CYCLES TO COMPLETE AND IS FULLY PIPELINED
SIGNAL DEFINITIONS
Power
Vcc and GND
+5V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
Inputs
AM
14-0
— Amplitude Modulation Data
Input
AM
14-0
is the 15-bit Amplitude
Modulation Data input port. AM
14-0
is latched on the rising edge of CLK.
PH
31-0
— Phase Angle Data Input
PH
31-0
is the 32-bit Phase Angle Data
input port. Input phase accumulators
are loaded through this port into
registers enabled by ENP
1-0
. PH
31-0
is
latched on the rising edge of CLK.
T
ABLE
1. R
EGISTER
O
PERATION
ENP
1-0
Configuration
00
01
10
11
No registers enabled, current data held
M register input enabled, C data held
C register input enabled, M data held
M register = 0, C register input enabled
T
ABLE
2. A
CCUMULATOR
C
ONTROL
FM PM Configuration
0
0
1
1
0
No accumulation (normal operation)
1
PM accumulator path enabled
0
FM accumulator path enabled
1
Logical OR of PM and FM (Nonsensical)
Special Arithmetic Functions
2
08/16/2000–LDS.2340-E