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LMU112JC50 参数 Datasheet PDF下载

LMU112JC50图片预览
型号: LMU112JC50
PDF下载: 下载PDF文件 查看货源
内容描述: 12× 12位并行乘法器 [12 x 12-bit Parallel Multiplier]
分类和应用:
文件页数/大小: 6 页 / 49 K
品牌: LOGIC [ LOGIC DEVICES INCORPORATED ]
 浏览型号LMU112JC50的Datasheet PDF文件第1页浏览型号LMU112JC50的Datasheet PDF文件第2页浏览型号LMU112JC50的Datasheet PDF文件第3页浏览型号LMU112JC50的Datasheet PDF文件第5页浏览型号LMU112JC50的Datasheet PDF文件第6页  
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*D
ISCONTINUED
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PEED
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RADE
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Min
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Min
DEVICES INCORPORATED
S
WITCHING
W
AVEFORMS
M
ILITARY
O
PERATING
R
ANGE
(–55°C to +125°C)
Notes 9, 10 (ns)
C
OMMERCIAL
O
PERATING
R
ANGE
(0°C to +70°C)
Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
t
DIS
t
ENA
t
D
t
H
t
S
t
PW
t
MC
t
DIS
t
ENA
t
D
t
H
t
S
t
PW
t
MC
INPUT
CLK B
CLK A
R
23-8
OE
Parameter
Parameter
Three-State Output Disable Delay
(Note 11)
Three-State Output Enable Delay
(Note 11)
Output Delay
Input Register Hold Time
Input Register Setup Time
Clock Pulse Width
Clocked Multiply Time
Three-State Output Disable Delay
(Note 11)
Three-State Output Enable Delay
(Note 11)
Output Delay
Input Register Hold Time
Input Register Setup Time
Clock Pulse Width
Clocked Multiply Time
t
S
t
H
t
DIS
HIGH IMPEDANCE
t
MC
4
t
PW
t
ENA
12 x 12-bit Parallel Multiplier
15
20
15
15
3
3
60*
65*
t
PW
Max
Max
25
25
25
60
30
30
30
65
t
D
Min
LMU112–
50
Min
15
20
15
15
3
3
LMU112–
55*
Max
Max
30
30
30
25
25
25
55
50
Multipliers
LMU112
Min
Min
08/16/2000–LDS.112-K
12
10
12
10
3
1
30*
25
Max
Max
25
25
25
20
20
20
30
25