80220/80221
1.0 Pin Description
Pin
44L 64L Name
28
24
11
10
1
44
27
23
36
9
4
41
42
43
2
3
40
37
29
32
25
8
7
57
56
31
23
41
6
60
52
54
55
58
59
50
42
34
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
GND6
GND5
GND4
GND3
GND2
GND1
TPO+
TPO -
TPI+
TPI -
REXT
OSCIN
TX_CLK
Pin#
I/O
—
Description
Positive Supply.
5
±
5% Volts
—
Ground.
0 Volts
O
O
I
I
—
I
O
Twisted Pair Transmit Output, Positive.
Twisted Pair Transmit Output, Negative.
Twisted Pair Receive Input, Positive.
Twisted Pair Receive Input, Negative.
Transmit Current Set.
An external resistor connected between this pin and GND will set the
output current level for the twisted pair outputs.
Clock Oscillator Input.
There must be either a 25 Mhz crystal between this pin and GND or
a 25 Mhz clock applied to this pin. TX_CLK output is generated from this input.
Transmit Clock Output.
This controller interface output provides a clock to an external
controller. Transmit data from the controller on TXD, TX_EN, and TX_ER is clocked in on
rising edges of TX_CLK and OSCIN.
Transmit Enable Input.
This controller interface input has to be asserted active high to
indicate that data on TXD and TX_ER is valid, and it is clocked in on rising edges of TX_CLK
and OSCIN.
Transmit Data Input.
These controller interface inputs contain input nibble data to be
transmitted on the TP outputs, and they are clocked in on rising edges of TX_CLK and OSCIN
when TX_EN is asserted.
Transmit Error Input.
This controller interface input causes a special pattern to be
transmitted on the twisted pair outputs in place of normal data, and it is clocked in on rising
edges of TX_CLK when TX_EN is asserted.
If the device is placed in the Bypass 4B5B Encoder mode, this pin is reconfigured to be the
fifth TXD transmit data input, TXD4.
35
40
TX_EN
I
33
32
31
30
34
38
37
36
35
39
TXD3
TXD2
TXD1
TXD0
TX_ER /
TXD4
I
I
25
26
RX_CLK
O
Receive Clock Output.
This controller interface output provides a clock to an external
controller. Receive data on RXD, RX_DV, and RX_ER is clocked out on falling edges of
RX_CLK.
Carrier Sense Output.
This controller interface output is asserted active high when valid data
is detected on the receive twisted pair inputs, and it is clocked out on falling edges of RX_CLK.
Receive Data Valid Output.
This controller interface output is asserted active high when valid
decoded data is present on the RXD outputs, and it is clocked out on falling edges of RX_CLK.
Receive Data Output.
These controller interface outputs contain receive nibble data from
the TP input, and they are clocked out on falling edges of RX_CLK.
16
17
19
20
21
22
13
14
19
20
21
22
CRS
RX_DV
RXD3
RXD2
RXD1
RXD0
O
O
O
4-5
5
MD400159/E
LSI [ LSI COMPUTER SYSTEMS ]
