XTLOUT
Crystal Out
Output
This signal provides a buffered clock reference frequency
for driving the L64734 XOIN pin.
Control Signals
The following signals, some of which are generated by the L64734 IC,
control the mode of operation of the L64733 IC.
AGC1
Automatic Gain Control 1
Input
The AGC1 signal is a high-impedance input from the
L64734; it controls the RF AGC circuitry. The AGC1
voltage range is from 0.5 V to 4.8 V.
AGC2
Automatic Gain Control 2
Input
The AGC2 signal is a high-impedance input from the
L64734; it controls RF AGC circuitry.
CPG[2:1]
Charge Pump Gain
Input
The CPG[2:1] signals set the charge pump gain
according to the following table.
Charge Pump Current (typ), mA
CPG1
CPG2
FB HIGH
FB LOW
0
0
1
1
0
1
0
1
0.1
0.3
0.6
1.8
−0.1
−0.3
−0.6
−1.8
FDOUB
Frequency Doubler
Input
When the FDOUB signal is asserted, the L64733 local
oscillator frequency is internally doubled and fed to the
mixers. When the FDOUB signal is deasserted, the
oscillator frequency is not doubled before being fed to the
mixers.
FLCLK
Filter Clock
Input
The FLCLK signal is a low-amplitude, self-biased clock
input. The frequency of the FLCLK signal multiplied by 16
is the baseband filter’s −3 dB frequency.
IDCn, IDCp
I-Channel DC Offset Correction
Input
Connect a 0.1 µF (or larger) capacitor between the IDCp
and IDCn signals.
10
L64733/L64734 Tuner and Satellite Receiver Chipset
LSI [ LSI COMPUTER SYSTEMS ]
