TRFADJ[1:0]
REXT
MCLK
100BTX TRANSMITTER
MDINT (MDA4)
SERIAL PORT
(MI)
DESCRAMBLER
AUTO-
NEGOTIATION
PLED[3:0]
(MDA[3:0])
LED
DRIVERS
SQUELCH
10BT RECEIVER
+/– Vth
PLED[5:4][1]
VCC[6:1]
CLOCK & DATA
RECOVERY
(MANCHESTER
DECODER)
GND[6:1]
Note 1: These pins available on 64L 80221 version only.
80220/80221
Figure 1. 80220 / 80221 Block Diagram
–
+
+
–
+
+
MD400159/E
+
TPO+
TPO–
–
4B5B
ENCODER
SCRAMBLER
LP
FILTER
MLT3
ENCODER
SWITCHED
CURRENT
SOURCES
OSCIN
OSCILLATOR
T4ADV [1]
[1]
T4OE
[1]
T4LNKI
CLOCK
GEN
(PLL)
2.0 Block Diagram
100BASET4
INTERFACE
RX_EN/JAM
RPTR [1]
10BT TRANSMITTER
TX_CLK
+
–
TXD[3:0]
MANCHESTER
ENCODER
ROM
DAC
LP
FILTER
TX_EN
TX_ER/TXD4
CONTROLLER
INTERFACE
(MII)
COL
COLLISION
CLOCK
GEN
(PLL)
RX_CLK
RXD[3:0]
4-9
9
SQUELCH
4B5B
DECODER
CLOCK & DATA
RECOVERY
CRS
RX_DV
100BTX RECEIVER
+/– Vth
TPI+
MLT3
ENCODER
ADAPTIVE
EQUALIZER
TPI–
RX_ER/RXD4
MDC
MDIO
LP
FILTER
LSI [ LSI COMPUTER SYSTEMS ]
