Table 4
LR4102 Register Memory Map (Cont.)
Register Name Physical Address
FBus registers (Cont.)
Description
FACFG2
FACFG3
FACFG4
FACFG5
FBUSTA
FACMP0
FACMP1
FACMP2
FACMP3
FACMP4
FACMP5
FBUSCMP
FBUSAC
0x1FFF.0408
0x1FFF.040C
0x1FFF.0410
0x1FFF.0414
0x1FFF.0418
0x1FFF.0440
0x1FFF.0444
0x1FFF.0448
0x1FFF.044C
0x1FFF.0450
0x1FFF.0454
0x1FFF.0470
0x1FFF.0474
Configuration for address range 2
Configuration for address range 3
Configuration for address range 4
Configuration for address range 5
Bus turnaround register for address range 0–5
Address compare register address range 0
Address compare register address range 1
Address compare register address range 2
Address compare register address range 3
Address compare register address range 4
Address compare register address range 5
Address compare register for FBus address range.
Address compare register for FBus I/O, memory, and
configuration address range.
FBUSCFG
0x1FFF.0480
Configuration for FBus when accessing outside
programmable address range 0–5.
FSDRAM
0x1FFF.0490
0x1FFF.0494
0x1FFF.0498
0x1FFF.04C0
0x1FFF.04C4
0x1FFF.04C8
Configuration for external EDO (S)DRAM
Timing parameters for external EDO DRAM
Timing parameters for external SDRAM
Configuration for General-Purpose I/O
Output value for General-Purpose Outputs
Input value for General-Purpose Inputs
FDRAMT
FSDRAMT
FGPCFG
FGPOUTPUT
FGPINPUT
Reserved registers
Reserved
0x1FFF.0500–.06FF Reserved for LSI Logic use
On Chip Memory (OCM), 1 Kbytes
OCM area
0x1FFF.8000–.83FF On chip memory. Placed on CBus, 1 cycle access
(Sheet 2 of 2)
12
TinyRISC LR4102 Microprocessor
LSI [ LSI COMPUTER SYSTEMS ]
