The EJTAG with PC Trace output provides real-time program counter
(PC) trace and breakpoint capability in an EJTAG compatible debug
design. PC trace outputs are provided through the Extended Debug
MACRO for complete and accurate chip debug. A SerialICE-1 Port
(UART) is also included in the LR4102 to provide backward compatibility
with previous TinyRISC designs.
Pipeline Architecture
The LR4102 implements a 3-stage pipeline (Fetch, Execute, and
Writeback) that uses a single adder for the ALU, the data address, and
the instruction address. Sharing a single adder dramatically reduces the
circuitry required to implement the microprocessor, and eliminates
pipeline registers and bypass logic. The LR4102 design does not require
a load delay slot.
Figure 2
shows the microprocessor CPU 3-stage
pipeline.
Figure 2
LR4102 CPU Pipeline with X2 Stall Cycle
IF
X1
X2
Stall
WB
Instruction Fetch
Execute
Writeback
The execution of a single LR4102 instruction consists of the following
three pipeline stages:
1. Instruction Fetch – The LR4102 fetches the instruction (IF), and if
necessary, decompresses a 16-bit instruction into a 32-bit
instruction.
2. Execute – The LR4102 executes all ALU instructions, resolves
conditional branches, and calculates load and store addresses (X1).
The CPU then transfers load or store data from external memory or
cache and performs move to/from coprocessor operations in a second
execute (stall) cycle (X2), which is only inserted when required.
3. Writeback – The LR4102 writes the results into the register file (WB).
4
TinyRISC LR4102 Microprocessor
LSI [ LSI COMPUTER SYSTEMS ]
