LSI/CSI
UL
®
LS7031
(631) 271-0400 FAX (631) 271-0405
December 2002
CONNECTION DIAGRAM - TOP VIEW
SCAN RESET INPUT
MSD STROBE 8
ST R OBE 7
ST R OBE 6
ST R OBE 5
DIGIT
STROBE
OUTPUTS
ST R OBE 4
ST R OBE 3
ST R OBE 2
LSD STROBE 1
DECIMAL POINT INPUT
BLANK OUTPUT
1
2
3
4
5
6
7
8
9
10
11
LS7031
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OSC. INPUT
SCAN INPUT
N.C.
B1/D1
B2/D1
N.C.
B4/D1
B8/D1
N.C.
B1/D2
B2/D2
B4/D2
B8/D2
V
SS
V
GG
N.C.
N.C.
V
DD
RESET COUNTER INPUT
LOAD LATCH INPUT
INPUT TO
DECADE 2
LATCH
INPUT TO
DECADE 1
LATCH
LSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
6 DECADE MOS UP COUNTER WITH 8 DECADE LATCH AND MULTIPLEXER
FEATURES:
• DC to 7.5 MHz Count Frequency
• Multiplexed BCD Outputs
• DC to 500kHz Scan Frequency
• +4.75V to +15V Operation (V
DD
-V
SS
)
• Compatible with CMOS Logic
• High Input Noise Immunity
• Ability to Latch External BCD Data in the two LSD Positions
• Leading Zero Blanking with Decimal Point and Overflow Controls
• All inputs protected
• Low Power Dissipation
• 40 Pin DIP - See Figure 1
DESCRIPTION:
The LS7031 is a monolithic, ion implanted MOS, 6 decade up coun-
ter. The circuit includes latches, a multiplexer, leading zero blanking
and BCD data outputs.
CLOCK GENERATOR
The clock for the six decade counter (digit positions 3-8) is formed
from the internal ‘OR’ combination of B4/D2 and B8/D2 if LS7031
is used with external prescaling counters. When operated in this
fashion the maximum allowable propagaton delay between B4/D2
(H-L) and B8/D2 (L-H), measured at Vss - 1V, is 10ns. If used as
a straight six decade counter, clock pulses may be applied to
in-
puts B4/D2 or B8/D2 with the unused input held low. In either mode
of operation total pulse width must be minimum 62ns. See Block
Diagram.
6 DECADE UP COUNTER
The six decade ripple through counter increments on the negative
edge of the input count pulse. Maximum ripple time is 12µs
(999999 to 000000). Maximum count frequency is 7.5MHz.
OVERFLOW OUTPUT 12
OVERFLOW INPUT 13
DECADE 8 OUTPUT,
DECADE 7 OUTPUT,
DECADE 6 OUTPUT,
D8
D7
D6
B8
BCD
DATA
OUTPUTS
B4
B2
B1
14
15
16
17
18
19
20
FIGURE 1
DIGIT STROBES
Timing of Digit Strobes is arranged such that both edges of strobe
are guardbanded by a minimum 400ns within valid BCD data when
scan frequency is 100kHz or less. The guardband is a minimum of
RESET
200ns at 250kHz scan frequency. At 500kHz only negative edge of
All 6 counter decades are reset to zero when Reset input is brought Strobe is guaranteed to be within valid BCD data by a minimum
low for a minimum of 4µs. The Overflow flip-flop is reset at the
200ns.
same time. Reset must be high for a minimum of 1µs before next
valid count can be recorded.
OVERFLOW
The Overflow flip-flop sets on the first negative transition of the Over-
SCAN OSCILLATOR AND COUNTER
flow Input and remains set until Reset is brought low. Data is trans-
The scan counter is driven by an internal oscillator whose
ferred from Overflow flip-flop to Overflow Latch when Load is brought
frequency is determined by a capacitor connected between
low. A high at the Overflow Latch causes display to unblank. Over-
Oscillator input and Scan input. An external scan clock applied
flow Output is output of Overflow Latch. MSB outputs of Decades
to Scan input can also drive the scan counter. Scan counter
6, 7, 8 are available for use as Overflow Input.
advances on negative edge of scan clock.
The counter scans from MSD to LSD. When Scan Reset input is
LATCHES
brought high the scan counter is forced to MSD state. Internal
Eight decades of latch are provided, two for storage of the two
synchonization guarantees proper scanning no matter when Scan external least significant decade counters and the remaining 6 for in-
Reset is brought low relative to scan clock. Maximum scan
ternal counter outputs. All latches when Load signal is brought low
frequency is 500kHz.
for a minimum of 4µs and kept low until a minimum of 12µs has
elapsed from previous negative edge of count pulse (ripple time).
DECIMAL POINT
Storage of valid data occurs when Load signal is high for a minimum
A high at the Decimal Point input resets the Blanking flip-flop
of 1µs before next negative edge of count pulse or reset. Data is
causing the display to unblank. Decimal Point should be brought
transferred from Overflow flip-flop to Overflow latch at the same time.
high at start of digit time which has active Decimal Point.
7031-121102-1
LSI [ LSI COMPUTER SYSTEMS ]
