T
PW
A
B
UPCK
(x1/7083)
DNCK
(x1/7083)
UPCK
(x4/7083)
DNCK
(x4/7083)
CLK
(x1/7084)
CLK
(x4/7084)
UP/DN
(7084)
T
PS
T
DS
T
OW
T
DS
FIGURE 2. LS7083/LS7084 INPUT/OUTPUT TIMING DIAGRAM
RBIAS
1
CURRENT
MIRROR
A
4
FILTER
DUAL
ONE-SHOT
CLOCK
AND
DIRECTION
DECODE
x4 CLOCK
8
x1 CLOCK
MUX
7 DNCK or UP/DN
UPCK or CLK
B
5
FILTER
DUAL
ONE-SHOT
UP/DN
x4/x1
V
DD
6
2
+V
-V
V
SS
3
FIGURE 3. LS7083/LS7084 BLOCK DIAGRAM
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
7083/84-100100-3
LSI [ LSI COMPUTER SYSTEMS ]
