LTCR
T
LC
T
LCW
T
CL
T
CH
UP CLK (A)
T
UDD
T
CH
T
CL
DN CLK (B)
Q0
(Internal)
Q1
(Internal)
Q2-Q23
(Internal)
CNTR=FFFFFD
(PR=CNTR)
CNTR=FFFFFE CNTR=FFFFFF CNTR=000000 CNTR=0000001 CNTR=000000 CNTR=FFFFFF CNTR=FFFFFE CNTR=FFFFFD
(PR=CNTR)
COMP
CY
BW
NOTE 2
FIGURE 2 . LOAD COUNTER, UP CLOCK, DOWN CLOCK, COMPARE OUT, CARRY, BORROW
NOTE 1:
The counter in this example is assumed to be operating in the binary mode.
NOTE 2:
No COMP output is generated here, although PR = CNTR. COMP output is disabled with a counter load command and
enabled with the rising edge of the next clock, thus eliminating invalid COMP outputs whenever the CNTR is loaded from the PR.
NOTE 3:
When UP Clock is active, the DN Clock should be held "HIGH" and vice versa.
UP CLK
OR DN CLK
T
CBH
T
CBL
CY
T
TFH
T
TFL
CYT
T
CBL
BW
T
CBH
T
TFL
T
TFH
BWT
T
CBL
T
CBH
COMP
T
TFH
COMPT
SIGN
(INTERNAL)
T
TFL
FIGURE 3. CLOCK TO CY/BW OUTPUT PROPAGATION DELAYS
7166-030192-7
LSI [ LSI COMPUTER SYSTEMS ]
