+V
3
1
2
A
B
V
DD
WB0
WB1
ƒi
+V
4
WB2
CLOCK
LS7212N
RESET
TRIG
OUT
WB3
WB4
WB5
WB6
WB7
Vss
8
17
16
15
14
13
12
11
10
7
18
9
ƒo
CASE 1. MODE = DO or DR; PRESCALE FACTOR, S = 1
In this setup a frequency division of the input clock, ƒi by a factor of 2 to 257, in increments of 1 can
be obtained according to the equation:
ƒo =
ƒi
W+2
where W (weighting factor) = 0 to 255
The ƒo pulse width is non-symmetrical (non-50% duty -cycle)
CASE 2. MODE = DD; PRESCALE FACTOR, S = 1
In this setup a frequency division of the input clock, ƒi by a factor of 2 to 512, in increments of 2 can
be obtained according to the equation:
ƒo
=
ƒi
2 (W + 1)
where W (weighting factor) = 0 to 255
The ƒo pulse widths are symmetrical with 50% duty -cycle
EXAMPLES OF CASE 1 and CASE 2 FREQUENCY DIVISIONS WITH W = 2
ƒi
ƒo
Case 1, Mode = DO;
ƒo
Case 2, Mode = DD;
÷
4
÷
6
FIGURE 10. PROGRAMMABLE FREQUENCY DIVIDER
7211N-052606-8
LSI [ LSI COMPUTER SYSTEMS ]
