DYNAMIC ELECTRICAL CHARACTERISTICS:
(C
L
= 50pF, Input Rise and Fall Times = 20ns except for Clock,
unless otherwise specified.)
V
DD
MIN
MAX
Clock Input Frequency
4.5V
0
1.5
10V
0
4.0
15V
0
6.0
Clock Input Rise & Fall Times
Clock Input Rise & Fall Time,
C
L
= 15pF
Clock Output Propagation
Delay, C
L
= 15pF
Output Rise & Fall Times
4.5 to 15V
4.5V
10V
4.5V
10V
4.5V
10V
4.5V
10V
4.5V
10V
4.5V
10V
4.5V
10V
4.5V
10V
-
-
-
-
-
-
-
-
-
800
400
-
-
-
-
-
-
No Limit
140
70
300
150
400
200
1500
750
-
-
500
250
1400
700
800
400
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20pF
39pF
40pF
10M
100pF
PIN 5
UNIT
MHz
MHz
MHz
10M
PIN 6
FIGURE 2.
MINIMUM PARTS OSCILLATOR CIRCUIT
PIN 5
20M
Propagation Delay to Output
PIN 6
Reset Pulse Width
FIGURE 3.
TYPICAL OSCILLATOR CIRCUIT WITH TRIM -1 MHZ AND BELOW
PIN 5
50pF
10M
Reset Removal Time
Reset Propagation Delay
to Output
Select Input Setup Time
56pF
PIN 6
FIGURE 4.
TYPICAL OSCILLATOR CIRCUIT WITH TRIM - ABOVE 1 MHZ
V
DD
CLOCK
INPUT
SIGNAL
R1
5
V
DD
FIGURE 5. TYPICAL INPUT
If input signals are less than V
SS
or greater than
V
DD
, a series input resistor, R1, should be used to
limit the maximum input current to 2 milliamperes.
V
SS
3 STAGE INVERTING
AMPLIFIER
+V
CLOCK IN
OSCILLATOR
EXTERNAL
COMPONENTS
5
8
V
DD
FIGURE 6.
RDD 104 BLOCK DIAGRAM
-V
3
V
SS
R
CLOCK
GENERATOR
÷
10
÷
10
÷
10
÷
10
CLOCK OUT
6
RESET
DIVIDER SELECT-1
4
1
DECODER
1 OUT OF 4 SELECTOR
BUFFER
7
OUTPUT
DIVIDER SELECT-2
2
RDD104-011000-2
LSI [ LSI COMPUTER SYSTEMS ]
