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RED60 参数 Datasheet PDF下载

RED60图片预览
型号: RED60
PDF下载: 下载PDF文件 查看货源
内容描述: AC LINE分频器 [AC LINE FREQUENCY DIVIDERS]
分类和应用:
文件页数/大小: 2 页 / 39 K
品牌: LSI [ LSI COMPUTER SYSTEMS ]
 浏览型号RED60的Datasheet PDF文件第1页  
ELECTRICAL CHARACTERISTICS:
(TA = 25° unless otherwise specified)
TEST CONDITIONS:
Vss = OV
Output Capacitance Load = 15 pF
Input Rise and Fall times = 20 ns,
except clock Rise and Fall times
Input Capacitance = 5pF max (any input)
V
DD
Min Max
Quiescent Device Current
5V
-
10
10V
-
20
Output Voltage, Low Level
5V
-
0.0
10V
-
0.0
High Level
5V 4.99 -
10V 9.99 -
Clock Input Voltage, Low Level
5V
-
1
10V
-
2
High Level
5V
4
-
10V
8
-
Input Noise Immunity
(except clock)
5V
1.5
-
(Low and High)
10V
3.0
-
Output Drive Current
Full
N Channel Sink Current 4.5V 0.18 -
Temp. (Vout - Vss +.4v)
10V 0.45 -
Range
P Channel Sink Current 4.5V
0.3
-
(Vout - VDD -1)
10V 0.75 -
Clock Rise and Fall Time:
Clock Frequency
V
DD
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
E
MIN
MAX
No Maximum Limit
No Maximum Limit
DC
600
DC
1200
800
400
-
-
-
-
-
-
800
400
-
-
-
-
-
-
225
150
1500
750
300
150
-
-
1200
600
1400
700
E
UNITS
-
-
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Clock Pulse Width
Units
uA
uA
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
Output Rise and Fall Time
Propagation Delay to Output
Enable Set-up Time
Reset Pulse Width
Reset Removal Time
Reset Propagation Delay
to Output
PULSE SHAPER
E
CL IN 5
E
INPUT CLOCK GENERATOR
CL
CL
R
ENABLE
6
RESET
2
R
DS
VDD
VSS
DIVISION SELECT
+4.5V to +15V
GND
N/C
7
8
3
4
RED 5/6,50/60,
300/360,3000/3600
1
D5/6
DS
1
CL1
CL
3 BIT
JOHNSON
+5/6
CL1
3 BIT
JOHNSON
÷10
CL2
CL2
3 BIT
JOHNSON
÷6
CL3
CL3
D50/60
CL
5 BIT
JOHNSON
÷10
1
D3000/3600
R
RED 100/120
DS
CL2
CL2
1 BIT
÷2
1
D300/360
CL
CL
3 BIT
JOHNSON
+5/6
CL1
CL1
5 BIT
JOHNSON
÷10
1
D100/120
R
RED 500/600
DS
CL
3 BIT
JOHNSON
+5/6
CL1
CL1
5 BIT
JOHNSON
÷10
CL2
CL2
CL
5 BIT
JOHNSON
÷10
1
D500/600
R
FIGURE 2. BLOCK DIAGRAM
RED-062600-2