71M6543F/H and 71M6543G/GH Data Sheet
10 11 12 13 14 15
SEGDIO
Pin #
0
1
2
3
4
5
6
7
8
9
45 44 43 42 41 39 38 37 36 35
34
33 32 31 30 29
Internal Resources
Configurable
–
–
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
–
–
–
–
(see Table 47)
The configuration for pins SEGDIO16 to SEGDIO31 is shown in Table 49, and the configuration for pins
SEGDIO32 to SEGDIO45 is shown in Table 50. The configuration for pins SEGDIO51 to SEGDIO55 is
shown in Table 51.
Table 49: Data/Direction Registers for SEGDIO16 to SEGDIO31
SEGDIO
Pin #
16
28
0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
27 25 24 23 22 21 20 19 18 17 16 11 10
9
8
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Configuration:
0 = DIO, 1 = LCD
LCD_MAP[23:16] (I/O RAM 0x2409)
LCD_MAP[31:24] (I/O RAM 0x2408)
16
16
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SEG Data Register
DIO Data Register
LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0]
(I/O RAM 0x2420[5:0] to 0x242F[5:0])
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LCD_SEGDIO16[0] to LCD_SEGDIO31[0]
(I/O RAM 0x2420[0] to 0x242F[0])
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Direction Register:
0 = input, 1 = output
LCD_SEGDIO16[1] to LCD_SEGDIO31[1]
(I/O RAM 0x2420[1] to 0x242F[1])
Table 50: Data/Direction Registers for SEGDIO32 to SEGDIO45
SEGDIO
Pin #
32
7
33 34 35 36
37 38 39 40 41 42 43 44 45
6
5
4
3
2
1
100 99 98 97 96 95 94
0
1
2
3
4
5
6
7
0
1
2
3
4
5
Configuration:
0 = DIO, 1 = LCD
LCD_MAP[39:32]
LCD_MAP[45:40]
(I/O RAM 0x2406[5:0])
37 38 39 40 41 42 43 44 45
LCD_SEGDIO32[5:0] to LCD_SEGDIO45[5:0]
(I/O RAM 0x2430[5:0] to 0x243D[5:0])
(I/O RAM 0x2407)
32
32
32
33 34 35 36
SEG Data Register
DIO Data Register
33 34 35 36
37 38 39 40 41 42 43 44 45
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RAM 0x2430[0] to 0x243D[0])
33 34 35 36
37 38 39 40 41 42 43 44 45
Direction Register:
0 = input, 1 = output
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RAM 0x2430[1] to 0x243D[1])
Table 51: Data/Direction Registers for SEGDIO51 to SEGDIO55
SEGDIO
Pin #
51
53
3
52 53 54 55
52 51 47 46
–
–
–
4
5
6
7
–
–
–
Configuration:
0 = DIO, 1 = LCD
LCD_MAP[55:48]
(I/O RAM 0x2405)
SEG Data Register
51
52 53 54 55
–
–
–
v1.2
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