DS1307 64 x 8, Serial, I
2
C Real-Time Clock
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. Table 2 shows the RTC
registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the
time and calendar registers are in the BCD format. The day-of-week register increments at midnight. Values that
correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on.) Illogical time and date entries result in undefined operation. Bit 7 of Register 0 is the clock halt
(CH) bit. When this bit is set to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. On first
application of power to the device the time and date registers are typically reset to 01/01/00 01 00:00:00
(MM/DD/YY DOW HH:MM:SS). The CH bit in the seconds register will be set to a 1. The clock can be halted
whenever the timekeeping functions are not required, which minimizes current (I
BATDR
).
The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or
24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with
logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). The hours value must be
re-entered whenever the 12/24-hour mode bit is changed.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the
internal registers on any I
2
C START. The time information is read from these secondary registers while the clock
continues to run. This eliminates the need to re-read the registers in case the internal registers update during a
read. The divider chain is reset whenever the seconds register is written. Write transfers occur on the I
2
C
acknowledge from the DS1307. Once the divider chain is reset, to avoid rollover issues, the remaining time and
date registers must be written within one second.
Table 2. Timekeeper Registers
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h–3Fh
0 = Always reads back as 0.
BIT 7
CH
0
0
0
0
0
OUT
BIT 6
BIT 5
BIT 4
10 Seconds
10 Minutes
10
12
10
Hour
Hour
PM/
24
AM
0
0
0
0
10 Date
10
0
0
Month
10 Year
0
0
SQWE
BIT 3
BIT 2
BIT 1
Seconds
Minutes
Hours
BIT 0
FUNCTION
Seconds
Minutes
Hours
Day
Date
Month
Year
Control
RAM
56 x 8
RANGE
00–59
00–59
1–12
+AM/PM
00–23
01–07
01–31
01–12
00–99
—
00h–FFh
0
DAY
Date
Month
Year
0
RS1
0
RS0
8 of 14
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
