DS1337 I2C Serial Real-Time Clock
AC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V to 5.5V, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast mode
100
0
400
100
SCL Clock Frequency
fSCL
kHz
Standard mode
Fast mode
1.3
Bus Free Time Between a
STOP and START Condition
tBUF
µs
µs
µs
Standard mode
Fast mode
4.7
0.6
4.0
1.3
4.7
Hold Time (Repeated)
START Condition (Note 10)
tHD:STA
Standard mode
Fast mode
LOW Period of SCL Clock
HIGH Period of SCL Clock
tLOW
tHIGH
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
0.6
4.0
0.6
4.7
0
0
100
250
µs
µs
Setup Time for a Repeated
START Condition
tSU:STA
tHD:DAT
tSU:DAT
tR
Data Hold Time
(Notes 11, 12)
0.9
µs
ns
ns
Data Setup Time (Note 13)
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
0.6
300
1000
300
Rise Time of Both SDA and
SCL Signals (Note 14)
Fall Time of Both SDA and
SCL Signals (Note 14)
tF
ns
300
Setup Time for STOP
Condition
Capacitive Load for Each Bus
Line
tSU:STO
CB
µs
pF
pF
4.0
(Note 14)
(Note 15)
400
10
I/O Capacitance (SDA, SCL)
CI/O
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Limits at -40°C are guaranteed by design and are not production tested.
SCL only.
SDA, INTA, and SQW/INTB.
ICCA—SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = VCC.
Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC.
SQW enabled.
Specified with the SQW function disabled by setting INTCN = 1.
Using recommended crystal on X1 and X2.
The device is fully accessible when 1.8 ≤ VCC ≤ 5.5V. Time and date are maintained when 1.3V ≤ VCC ≤ 1.8V.
After this period, the first clock pulse is generated
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12:
Note 13:
The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
Note 14:
Note 15:
CB—total capacitance of one bus line in pF.
Guaranteed by design. Not production tested.
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