250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS (continued)
(V
DD
= V
LOGIC
= +2.7V to +3.6V, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 4.8MHz (50% duty
cycle); T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
RD
Rise to Output Disable
RD
Fall to Output Data Valid
HBEN to Output Data Valid
RD
Fall to
INT
High Delay
CS
Fall to Output Data Valid
SYMBOL
t
TR
t
DO
t
DO1
t
INT1
t
DO2
CONDITIONS
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
MIN
20
20
20
TYP
MAX
70
70
110
100
110
UNITS
ns
ns
ns
ns
ns
MAX1291/MAX1293
Note 1:
Tested at V
DD
= +3V, COM = GND, unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3:
Offset nulled.
Note 4:
On channel is grounded; sine wave applied to off channels.
Note 5:
Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:
Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V
DD
.
Note 7:
External load should not change during conversion for specified accuracy.
Note 8:
When bit 5 is set low for internal acquisition,
WR
must not return low until after the first falling clock edge of the conversion.
V
LOGIC
3k
DOUT
3k
GND
a)
HIGH-Z TO V
OH
AND V
OL
TO V
OH
C
LOAD
20pF
DOUT
C
LOAD
20pF
GND
b)
HIGH-Z TO V
OL
AND V
OH
TO V
OL
Figure 1. Load Circuits for Enable/Disable Times
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5
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
