Hig h -Effic ie n c y, P WM, S t e p -Do w n
DC-DC Co n t ro lle rs in 1 6 -P in QS OP
2–MAX165
VL
R1
R2
TO PWM
LOGIC
UNCOMPENSATED
HIGH-SPEED
FB
LEVEL TRANSLATOR
AND BUFFER
OUTPUT DRIVER
I1
I2
I3
REF
CSH
CSL
SLOPE COMPENSATION
Figure 4. Main PWM Comparator Block Diagram
In discontinuous (light-load) mode, the synchronous
switch is turned off as the inductor current falls through
zero. The synchronous rectifier works under all operat-
ing conditions, including idle mode. The synchronous-
switch timing is further controlled by the secondary
feedback (SECFB) signal in order to improve multiple-
output cross-regulation (see Secondary Feedback-
Regulation Loop section).
When the main output voltage is above 4.5V, an internal
P-channel MOSFET switch connects CSL to VL while
simultaneously shutting down the VL linear regulator.
This action bootstraps the IC, powering the internal cir-
cuitry from the output voltage, rather than through a lin-
ear regulator from the battery. Bootstrapping reduces
power dissipation caused by gate-charge and quies-
cent losses by providing that power from a 90%-effi-
c ie nt s witc h-mod e s ourc e , ra the r tha n from a le s s
efficient linear regulator.
In t e rn a l VL a n d REF S u p p lie s
An internal regulator produces the 5V supply (VL) that
powers the PWM controller, logic, reference, and other
blocks. This +5V low-dropout linear regulator can sup-
ply up to 5mA for external loads, with a reserve of
20mA for gate-drive power. Bypass VL to GND with
4.7µF. Important: VL must not be allowed to exceed
5.5V. Measure VL with the main output fully loaded. If
VL is b e ing p ump e d up a b ove 5.5V, the p rob a b le
cause is either excessive boost-diode capacitance or
excessive ripple at V+. Use only small-signal diodes for
D2 (10mA to 100mA Schottky or 1N4148 are preferred)
a nd b yp a ss V+ to PGND with 0.1µF dire c tly a t the
package pins.
It’s often possible to achieve a bootstrap-like effect,
even for circuits that are set to V
< 4.5V, by power-
OUT
ing VL from an external-system +5V supply. To achieve
this pseudo-bootstrap, add a Schottky diode between
the external +5V source and VL, with the cathode to the
VL side. This circuit provides a 1% to 2% efficiency
boost and also extends the minimum battery input to
less than 4V. The external source must be in the range
of 4.8V to 5.5V.
Bo o s t Hig h -S id e
Ga t e -Drive r S u p p ly (BS T P in )
Gate-drive voltage for the high-side N-channel switch is
generated by a flying-capacitor boost circuit as shown
in Figure 5. The capacitor is alternately charged from
the VL supply and placed in parallel with the high-side
MOSFET’s gate-source terminals.
The 2.5V reference (REF) is accurate to ±1.6% over
temperature, making REF useful as a precision system
reference. Bypass REF to GND with 0.33µF minimum.
REF can supply up to 1mA for external loads. However,
if tig ht-a c c ura c y s p e c s for e ithe r V
or REF a re
OUT
On start-up, the synchronous rectifier (low-side MOS-
FET) forces LX to 0V and charges the BST capacitor to
5V. On the second half-cycle, the PWM turns on the
hig h-s id e MOSFET b y c los ing a n inte rna l s witc h
between BST and DH. This provides the necessary
enhancement voltage to turn on the high-side switch,
essential, avoid loading REF with more than 100µA.
Loading REF reduces the main output voltage slightly,
a c c ord ing to the re fe re nc e -volta g e loa d re g ula tion
error. In MAX1654 applications, ensure that the SECFB
divider doesn’t load REF heavily.
______________________________________________________________________________________ 15
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
