19-3781; Rev 0; 8/05
USB Peripheral Controller
with SPI Interface
General Description
The MAX3420E contains the digital logic and analog
circuitry necessary to implement a full-speed USB
peripheral compliant to USB specification rev 2.0. A
built-in full-speed transceiver features ±15kV ESD pro-
tection and programmable USB connect and discon-
nect. An internal SIE (serial-interface engine) handles
low-level USB protocol details such as error checking
and bus retries. The MAX3420E operates using a regis-
ter set accessed by an SPI interface that operates up to
26MHz. Any SPI master (microprocessor, ASIC, DSP,
etc.) can add USB functionality using the simple 3- or
4-wire SPI interface.
Internal level translators allow the SPI interface to run at
a system voltage between 1.71V and 3.6V. USB timed
operations are done inside the MAX3420E with inter-
rupts provided at completion so an SPI master does not
need timers to meet USB timing requirements. The
MAX3420E includes four general-purpose inputs and
outputs so any microprocessor that uses I/O pins to
implement the SPI interface can reclaim the I/O pins
and gain additional ones.
The MAX3420E operates over the extended -40°C to
+85°C temperature range and is available in a 32-pin
TQFP package (7mm x 7mm) and a space-saving 24-
pin TQFN package (4mm x 4mm).
Features
♦
Microprocessor-Independent USB Solution
♦
Complies with USB Specification Revision 2.0
(Full-Speed Operation)
♦
Integrated Full-Speed USB Transceiver
♦
Firmware/Hardware Control of an Internal D+
Pullup Resistor
♦
Programmable 3- or 4-Wire 26MHz SPI Interface
♦
Level Translators and V
L
Input Allow Independent
System Interface Voltage
♦
Internal Comparator Detects V
BUS
for
Self-Powered Applications
♦
ESD Protection on D+, D-, and VBCOMP
♦
Interrupt Output Pin (Level or Programmable
Edge) Allows Polled or Interrupt-Driven SPI
Interface
♦
Intelligent USB Serial Interface Engine (SIE)
Automatically Handles USB Flow Control and
Double Buffering
Handles Low-Level USB Signaling Details
Contains Timers for USB Time-Sensitive
Operations So SPI Master Does Not Need to
Time Events
♦
Built-In Endpoint FIFOs:
EP0: CONTROL (64 Bytes)
EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
EP2: IN, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
EP3: IN, Bulk or Interrupt (64 Bytes)
♦
Double-Buffered Data Endpoints Increase
Throughput by Allowing the SPI Master to
Transfer Data Concurrently with USB Transfers
Over the Same Endpoint
♦
SETUP Data Has Its Own 8-Byte FIFO, Simplifying
Firmware
♦
Four General-Purpose Inputs and Four General-
Purpose Outputs
♦
Space-Saving TQFP and TQFN Packages
MAX3420E
Applications
Cell Phones
PC Peripherals
Microprocessors and
DSPs
Custom USB Devices
Cameras
Desktop Routers
PLCs
Set-Top Boxes
PDAs
MP3 Players
Instrumentation
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
32 TQFP
7mm x 7mm x
1.4mm
24 TQFN
4mm x 4mm x
0.8mm
PACKAGE
CODE
C32-1
MAX3420EECJ -40°C to +85°C
MAX3420EETG* -40°C to +85°C
T2444-4
*Future product—contact factory for availability.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
