Low-Voltage, Single-Supply
Dual SPST/SPDT Analog Switches
_________________________________Test Circuits/Timing Diagrams (continued)
V+
MAX4543
+3V
LOGIC
50%
INPUT
V+
V
OUT1
COM1
COM2
NO1
0
+3V
V
OUT2
C
C
35pF
NC2
IN1
R
L1
SWITCH
L1
300Ω
0.9 · V
0UT1
OUTPUT 1
R
L2
300Ω
(V
OUT1
)
0
L2
35pF
IN2
LOGIC
INPUT
SWITCH
GND
0.9 · V
OUTPUT 2
OUT2
(V
OUT2
)
0
t
t
D
D
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
Figure 3a. Break-Before-Make Interval (MAX4543 only)
V+
MAX4544
+3V
0
LOGIC
INPUT
50%
V+
NC
V
+3V
OUT
COM
NO
R
L
C
L
300Ω
35pF
IN
LOGIC
INPUT
SWITCH
OUTPUT
GND
0.9 · V
OUT
(V
)
OUT
t
D
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
Figure 3b. Break-Before-Make Interval (MAX4544 only)
V+
∆V
OUT
MAX4541
MAX4542
MAX4543
MAX4544
V+
COM
V
OUT
R
GEN
NC
OR NO
V
OUT
IN
OFF
OFF
OFF
OFF
C
L
ON
ON
V
GEN
GND
IN_
IN
V
= +3V
Q = (∆V )(C )
IN
OUT
L
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge Injection
_______________________________________________________________________________________
8
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
