+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t
S e ria l 1 2 -Bit DACs
____________________P in De s c rip t io n
_______________De t a ile d De s c rip t io n
Ge n e ra l DAC Dis c u s s io n
PIN
The MAX531/MAX538/MAX539 use an “inverted” R-2R
ladder network with a single-supply CMOS op amp to con-
vert 12-bit digital data to analog voltage levels (see
Functional Diagram). The term “inverted” describes the
ladder network because the REFIN pin in current-output
DACs is the summing junction, or virtual ground, of an op
amp. However, such use would result in the output voltage
b e ing the inve rs e of the re fe re nc e volta g e . The
MAX531/MAX538/MAX539’s topology makes the output
the same polarity as the reference input.
NAME
FUNCTION
MAX538
MAX539
MAX531
Bipolar Offset/Gain
Resistor
—
1
BIPOFF
DIN
1
2
3
Serial Data Input
Clear. Asynchronously sets
DAC register to 000 hex.
—
CLR
An internal reset circuit forces the DAC register to reset to
000 hex on power-up. Additionally, a clear CLR pin, when
held low, sets the DAC register to 000 hex. CLR operates
asynchronously and independently from the chip-select
(CS) pin.
4
5
2
3
SCLK
Serial Clock Input
Chip Select, active low
CS
Serial Data Output for
daisy-chaining
6
4
DOUT
Bu ffe r Am p lifie r
7
8
9
—
5
DGND
AGND
REFIN
Digital Ground
Analog Ground
Reference Input
The output buffer is a unity-gain stable, rail-to-rail output,
BiCMOS op amp. Input offset voltage and CMRR are
trimmed to achieve better than 12-bit performance.
Settling time is 25µs to 0.01% of final value. The settling
time is considerably longer when the DAC code is initially
set to 000 hex, because at this code the op amp is com-
pletely debiased. Start from code 001 hex if necessary.
The output is short-circuit protected and can drive a 2kΩ
load with more than 100pF load capacitance.
6
18/MAX539
Reference Output,
2.048V
10
—
REFOUT
11
12
13
14
—
7
V
SS
Negative Power Supply
DAC Output
VOUT
8
V
DD
Positive Power Supply
Feedback Resistor
—
RFB
CS
t
t
CSH0
CSW
t
CH
t
t
CL
t
CSH1
CSS
SCLK
t
DH
t
CS1
t
DS
DIN
t
DO
DOUT
Figure 1. Timing Diagram
8
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
