Quad LVDS Line Driver
MAX9124
OUT_+
C
L
OUT_ +
R
L
/2
GND
R
L
/2
V
OS
V
OD
S
V
CC
IN_
V
O
GENERATOR
IN_
R
L
OUT_ -
C
L
50Ω
OUT_-
Figure 1. Driver V
OD
and V
OS
Test Circuit
Figure 2. Driver Propagation Delay and Transition Time Test
Circuit
3V
IN_
1.5V
1.5V
0
t
PLHD
OUT_ -
0 DIFFERENTIAL
OUT_+
0
V
OL
80%
V
DIFF
50%
20%
t
TLH
0
80%
V
DIFF
= (V
OUT_
+) - (V
OUT_
-)
0
20%
t
THL
t
PHLD
V
OH
Figure 3. Driver Propagation Delay and Transition Time Waveforms
C
L
OUT_+
V
CC
GND
GENERATOR
50Ω
1/4 MAX9124
C
L
EN
EN
R
L/2
OUT_-
+1.2V
IN_
R
L/2
Figure 4. Driver High-Impedance Delay Test Circuit
6
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