19-0547; Rev 3; 11/07
IT
TION K
VALUA
E
BLE
AVAILA
High-Precision Clock Generators
with Integrated VCXO
General Description
Features
♦
Integrated VCXO Provides a Cost-Effective
Solution for High-Precision Clocks
♦
8kHz to 500MHz Input Frequency Range
♦
15MHz to 160MHz Output Frequency Range
♦
I
2
C or SPI Programming for the Input and Output
Frequency Selection
♦
PLL Lock Range > ±60ppm
♦
Two Differential Outputs with Three Types of
Signaling: LVPECL, LVDS, or HSTL
♦
Input Clock Monitor with Hitless Switch
♦
Internal Holdover Function within ±20ppm of the
Nominal Frequency
♦
Low Output CLK Jitter: < 0.8ps RMS in the 12kHz
to 20MHz Band
♦
Low Phase Noise > -130dBc at 100kHz, > -140dBc
at 1MHz
MAX9450/MAX9451/MAX9452
The MAX9450/MAX9451/MAX9452 clock generators
provide high-precision clocks for timing in SONET/SDH
systems or Gigabit Ethernet systems. The MAX9450/
MAX9451/MAX9452 can also provide clocks for the high-
speed and high-resolution ADCs and DACs in 3G base
stations. Additionally, the devices can also be used as a
jitter attenuator for generating high-precision CLK signals.
The MAX9450/MAX9451/MAX9452 feature an integrated
VCXO. This configuration eliminates the use of an exter-
nal VCXO and provides a cost-effective solution for gen-
erating high-precision clocks. The MAX9450/MAX9451/
MAX9452 feature two differential inputs and clock out-
puts. The inputs accept LVPECL, LVDS, differential sig-
nals, and LVCMOS. The input reference clocks range
from 8kHz to 500MHz.
The MAX9450/MAX9451/MAX9452 offer LVPECL, HSTL,
and LVDS outputs, respectively. The output range is up
to 160MHz, depending on the selection of crystal. The
input and output frequency selection is implemented
through the I
2
C or SPI™ interface. The MAX9450/
MAX9451/MAX9452 feature clock output jitter less than
0.8ps RMS (in a 12kHz to 20MHz band) and phase-
noise attenuation greater than -130dBc/Hz at 100kHz.
The phase-locked loop (PLL) filter can be set externally,
and the filter bandwidth can vary from 1Hz to 20kHz.
The MAX9450/MAX9451/MAX9452 feature an input
clock monitor with a hitless switch. When a failure is
detected at the selected reference clock, the device
can switch to the other reference clock. The reaction to
the recovery of the failed reference clock can be
revertive or nonrevertive. If both reference clocks fail,
the PLL retains its nominal frequency within a range of
±20ppm at +25°C.
The MAX9450/MAX9451/MAX9452 operate from 2.4V to
3.6V supply and are available in 32-pin TQFP packages
with exposed pads.
Ordering Information
PART
MAX9450EHJ
MAX9451EHJ
MAX9452EHJ
PIN-PACKAGE
32 TQFP-EP*
32 TQFP-EP*
32 TQFP-EP*
OUTPUT
LVPECL
HSTL
LVDS
PKG CODE
H32E-6
H32E-6
H32E-6
Note:
All devices are specified over the -40°C to +85°C
temperature range.
For lead-free packages, contact factory.
*EP
= Exposed paddle.
Pin Configuration
CLK1+
CLK0+
CLK1-
V
DDQ
V
DDQ
18
GND
TOP VIEW
CLK0-
24
23
22
21
20
19
17
V
DD
25
X1 26
X2 27
V
DDA
28
LP1 29
LP2 30
GNDA 31
RJ 32
OE
16 CMON
15 AD1
14 AD0
13 SDA
12 SCL
11 GND/CS
10 MR
9
INT
8
IN1-
Applications
SONET/SDH Systems
10 Gigabit Network Routers and Switches
3G Cellular Phone Base Stations
General Jitter Attenuation
MAX9450
MAX9451
MAX9452
EXPOSED PAD
(GND)
1
LOCK
2
SEL0
3
SEL1
4
IN0+
5
IN0-
6
V
DD
7
IN1+
SPI is a trademark of Motorola, Inc.
TQFP
(5mm x 5mm)
1
________________________________________________________________
Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
